@@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
+#include <linux/irqchip/irq-davinci-cp-intc.h>
#include <linux/irqdomain.h>
#include <linux/io.h>
#include <linux/of.h>
@@ -144,22 +145,15 @@ static const struct irq_domain_ops davinci_cp_intc_irq_domain_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-static int __init davinci_cp_intc_of_init(struct device_node *node,
- struct device_node *parent)
+static int __init
+davinci_cp_intc_do_init(const struct davinci_cp_intc_config *config,
+ struct device_node *node)
{
- u32 num_irq = davinci_soc_info.intc_irq_num;
- u8 *irq_prio = davinci_soc_info.intc_irq_prios;
- unsigned num_reg = BITS_TO_LONGS(num_irq);
- int i, irq_base;
-
- if (node) {
- davinci_cp_intc_base = of_iomap(node, 0);
- if (of_property_read_u32(node, "ti,intc-size", &num_irq))
- pr_warn("unable to get intc-size, default to %d\n",
- num_irq);
- } else {
- davinci_cp_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
- }
+ unsigned int num_regs = BITS_TO_LONGS(config->num_irqs);
+ int offset, irq_base;
+
+ davinci_cp_intc_base = ioremap(config->reg.start,
+ resource_size(&config->reg));
if (WARN_ON(!davinci_cp_intc_base))
return -EINVAL;
@@ -169,51 +163,29 @@ static int __init davinci_cp_intc_of_init(struct device_node *node,
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_ENABLE(0));
/* Disable system interrupts */
- for (i = 0; i < num_reg; i++)
- davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_ENABLE_CLR(i));
+ for (offset = 0; offset < num_regs; offset++)
+ davinci_cp_intc_write(~0,
+ DAVINCI_CP_INTC_SYS_ENABLE_CLR(offset));
/* Set to normal mode, no nesting, no priority hold */
davinci_cp_intc_write(0, DAVINCI_CP_INTC_CTRL);
davinci_cp_intc_write(0, DAVINCI_CP_INTC_HOST_CTRL);
/* Clear system interrupt status */
- for (i = 0; i < num_reg; i++)
- davinci_cp_intc_write(~0, DAVINCI_CP_INTC_SYS_STAT_CLR(i));
+ for (offset = 0; offset < num_regs; offset++)
+ davinci_cp_intc_write(~0,
+ DAVINCI_CP_INTC_SYS_STAT_CLR(offset));
/* Enable nIRQ (what about nFIQ?) */
davinci_cp_intc_write(1, DAVINCI_CP_INTC_HOST_ENABLE_IDX_SET);
- /*
- * Priority is determined by host channel: lower channel number has
- * higher priority i.e. channel 0 has highest priority and channel 31
- * had the lowest priority.
- */
- num_reg = (num_irq + 3) >> 2; /* 4 channels per register */
- if (irq_prio) {
- unsigned j, k;
- u32 val;
-
- for (k = i = 0; i < num_reg; i++) {
- for (val = j = 0; j < 4; j++, k++) {
- val >>= 8;
- if (k < num_irq)
- val |= irq_prio[k] << 24;
- }
-
- davinci_cp_intc_write(val, DAVINCI_CP_INTC_CHAN_MAP(i));
- }
- } else {
- /*
- * Default everything to channel 15 if priority not specified.
- * Note that channel 0-1 are mapped to nFIQ and channels 2-31
- * are mapped to nIRQ.
- */
- for (i = 0; i < num_reg; i++)
- davinci_cp_intc_write(0x0f0f0f0f,
- DAVINCI_CP_INTC_CHAN_MAP(i));
- }
+ /* Default all priorities to channel 7. */
+ num_regs = (config->num_irqs + 3) >> 2; /* 4 channels per register */
+ for (offset = 0; offset < num_regs; offset++)
+ davinci_cp_intc_write(0x07070707,
+ DAVINCI_CP_INTC_CHAN_MAP(offset));
- irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
+ irq_base = irq_alloc_descs(-1, 0, config->num_irqs, 0);
if (irq_base < 0) {
pr_warn("Couldn't allocate IRQ numbers\n");
irq_base = 0;
@@ -221,7 +193,7 @@ static int __init davinci_cp_intc_of_init(struct device_node *node,
/* create a legacy host */
davinci_cp_intc_irq_domain = irq_domain_add_legacy(
- node, num_irq, irq_base, 0,
+ node, config->num_irqs, irq_base, 0,
&davinci_cp_intc_irq_domain_ops, NULL);
if (!davinci_cp_intc_irq_domain) {
@@ -237,9 +209,25 @@ static int __init davinci_cp_intc_of_init(struct device_node *node,
return 0;
}
-void __init davinci_cp_intc_init(void)
+int __init davinci_cp_intc_init(const struct davinci_cp_intc_config *config)
{
- davinci_cp_intc_of_init(NULL, NULL);
+ return davinci_cp_intc_do_init(config, NULL);
}
+static int __init davinci_cp_intc_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct davinci_cp_intc_config config = { };
+ int rv;
+
+ rv = of_address_to_resource(node, 0, &config.reg);
+ if (WARN_ON(rv))
+ return rv;
+
+ rv = of_property_read_u32(node, "ti,intc-size", &config.num_irqs);
+ if (WARN_ON(rv))
+ return rv;
+
+ return davinci_cp_intc_do_init(&config, node);
+}
IRQCHIP_DECLARE(cp_intc, "ti,cp-intc", davinci_cp_intc_of_init);
@@ -754,7 +754,7 @@ static const struct davinci_cp_intc_config da830_cp_intc_config = {
void __init da830_init_irqs(void)
{
- davinci_cp_intc_init();
+ davinci_cp_intc_init(&da830_cp_intc_config);
}
void __init da830_init_time(void)
@@ -683,7 +683,7 @@ static const struct davinci_cp_intc_config da850_cp_intc_config = {
void __init da850_init_irqs(void)
{
- davinci_cp_intc_init();
+ davinci_cp_intc_init(&da850_cp_intc_config);
}
void __init da850_init_time(void)
@@ -17,7 +17,6 @@
#include <linux/types.h>
#include <linux/reboot.h>
-void davinci_cp_intc_init(void);
void davinci_timer_init(struct clk *clk);
struct davinci_timer_instance {
@@ -13,4 +13,6 @@ struct davinci_cp_intc_config {
unsigned int num_irqs;
};
+int davinci_cp_intc_init(const struct davinci_cp_intc_config *config);
+
#endif /* _LINUX_IRQ_DAVINCI_CP_INTC_ */