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[2/4] Documentation: perf: Add documentation for arm-smmu-v3-pmcg

Message ID 20200712163341.61410-3-ajaykumar.rs@samsung.com (mailing list archive)
State New, archived
Headers show
Series Add DT support for arm_smmuv3_pmu driver | expand

Commit Message

Ajay Kumar July 12, 2020, 4:33 p.m. UTC
This patch adds devicetree binding for perf/arm_smmuv3_pmu driver.

Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>
---
 .../bindings/perf/arm-smmu-v3-pmcg.txt        | 21 +++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt

Comments

Jonathan Cameron July 13, 2020, 8:41 a.m. UTC | #1
On Sun, 12 Jul 2020 22:03:39 +0530
Ajay Kumar <ajaykumar.rs@samsung.com> wrote:

> This patch adds devicetree binding for perf/arm_smmuv3_pmu driver.
> 
> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com>

New bindings want to be in yaml format.

> ---
>  .../bindings/perf/arm-smmu-v3-pmcg.txt        | 21 +++++++++++++++++++
>  1 file changed, 21 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
> 
> diff --git a/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt b/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
> new file mode 100644
> index 000000000000..a20fe68ce149
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
> @@ -0,0 +1,21 @@
> +* ARM SMMU V3 PMCG
> +
> +Required properties:
> +
> +- compatible: should be "arm-smmu-v3-pmu"
> +
> +- reg: (standard registers property) physical address and size
> +	of the performance counters registers block.
> +	If Page 1 is present, specify the same.
> +
> +- interrupts: (standard interrupt property) single interrupt
> +	generated by the SMMU PMU control block
> +
> +Example:
> +
> +	pmcg@20002000 {
> +		compatible = "arm-smmu-v3-pmu";
> +		reg = <0x0 0x20002000 0x0 0x1000>,
> +			<0x0 0x20022000 0x0 0xE00>; /* Page 1 */
> +		interrupts = <0 181 4>;
> +	};
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt b/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
new file mode 100644
index 000000000000..a20fe68ce149
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/arm-smmu-v3-pmcg.txt
@@ -0,0 +1,21 @@ 
+* ARM SMMU V3 PMCG
+
+Required properties:
+
+- compatible: should be "arm-smmu-v3-pmu"
+
+- reg: (standard registers property) physical address and size
+	of the performance counters registers block.
+	If Page 1 is present, specify the same.
+
+- interrupts: (standard interrupt property) single interrupt
+	generated by the SMMU PMU control block
+
+Example:
+
+	pmcg@20002000 {
+		compatible = "arm-smmu-v3-pmu";
+		reg = <0x0 0x20002000 0x0 0x1000>,
+			<0x0 0x20022000 0x0 0xE00>; /* Page 1 */
+		interrupts = <0 181 4>;
+	};