| Message ID | 20220428230933.15262-3-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: sunxi: Initial Allwinner H616 SoC support | expand |
Dne petek, 29. april 2022 ob 01:09:29 CEST je Andre Przywara napisal(a): > The RTC section of the H616 manual mentions in a half-sentence the > existence of a clock "32K divided by PLL_PERI(2X)". This is used as > one of the possible inputs for the mux that selects the clock for the > 32 KHz fanout pad. On the H616 this is routed to pin PG10, and some > boards use that clock output to compensate for a missing 32KHz crystal. > On the OrangePi Zero2 this is for instance connected to the LPO pin of > the WiFi/BT chip. > The new RTC clock binding requires this clock to be named as one input > clock, so we need to expose this to the DT. In contrast to the D1 SoC > there does not seem to be a gate for this clock, so just use a fixed > divider clock, using a newly assigned clock number. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > Reviewed-by: Samuel Holland <samuel@sholland.org> Applied to sunxi/clk-for-5.19, thanks! Best regards, Jernej > --- > drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 8 ++++++++ > drivers/clk/sunxi-ng/ccu-sun50i-h616.h | 2 +- > include/dt-bindings/clock/sun50i-h616-ccu.h | 1 + > 3 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ ccu-sun50i-h616.c > index 49a2474cf314..21e918582aa5 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c > @@ -704,6 +704,13 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll- periph0-2x", > pll_periph0_parents, > 1, 2, 0); > > +static const struct clk_hw *pll_periph0_2x_hws[] = { > + &pll_periph0_2x_clk.hw > +}; > + > +static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", > + pll_periph0_2x_hws, 36621, 1, 0); > + > static const struct clk_hw *pll_periph1_parents[] = { > &pll_periph1_clk.common.hw > }; > @@ -852,6 +859,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = { > [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, > [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, > [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, > + [CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw, > [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, > [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, > [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/ ccu-sun50i-h616.h > index dd671b413f22..fdd2f4d5103f 100644 > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h > @@ -51,6 +51,6 @@ > > #define CLK_BUS_DRAM 56 > > -#define CLK_NUMBER (CLK_BUS_HDCP + 1) > +#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1) > > #endif /* _CCU_SUN50I_H616_H_ */ > diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt- bindings/clock/sun50i-h616-ccu.h > index 4fc08b0df2f3..1191aca53ac6 100644 > --- a/include/dt-bindings/clock/sun50i-h616-ccu.h > +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h > @@ -111,5 +111,6 @@ > #define CLK_BUS_TVE0 125 > #define CLK_HDCP 126 > #define CLK_BUS_HDCP 127 > +#define CLK_PLL_SYSTEM_32K 128 > > #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ > -- > 2.35.3 > >
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c index 49a2474cf314..21e918582aa5 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c @@ -704,6 +704,13 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_parents, 1, 2, 0); +static const struct clk_hw *pll_periph0_2x_hws[] = { + &pll_periph0_2x_clk.hw +}; + +static CLK_FIXED_FACTOR_HWS(pll_system_32k_clk, "pll-system-32k", + pll_periph0_2x_hws, 36621, 1, 0); + static const struct clk_hw *pll_periph1_parents[] = { &pll_periph1_clk.common.hw }; @@ -852,6 +859,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = { [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw, [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw, [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw, + [CLK_PLL_SYSTEM_32K] = &pll_system_32k_clk.hw, [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw, [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw, [CLK_PLL_GPU] = &pll_gpu_clk.common.hw, diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h index dd671b413f22..fdd2f4d5103f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.h +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.h @@ -51,6 +51,6 @@ #define CLK_BUS_DRAM 56 -#define CLK_NUMBER (CLK_BUS_HDCP + 1) +#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1) #endif /* _CCU_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 4fc08b0df2f3..1191aca53ac6 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -111,5 +111,6 @@ #define CLK_BUS_TVE0 125 #define CLK_HDCP 126 #define CLK_BUS_HDCP 127 +#define CLK_PLL_SYSTEM_32K 128 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */