diff mbox series

[v2,09/28] arm64/sysreg: Standardise naming of ID_AA64MMFR0_EL1.ASIDBits

Message ID 20220815162648.781802-10-broonie@kernel.org (mailing list archive)
State New, archived
Headers show
Series arm64/sysreg: More system register generation | expand

Commit Message

Mark Brown Aug. 15, 2022, 4:26 p.m. UTC 
For some reason we refer to ID_AA64MMFR0_EL1.ASIDBits as ASID. Add BITS
into the name, bringing the naming into sync with DDI0487H.a. Due to the
large amount of MixedCase in this register which isn't really consistent
with either the kernel style or the majority of the architecture the use of
upper case is preserved. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
---
 arch/arm64/include/asm/sysreg.h                | 6 +++---
 arch/arm64/kernel/cpufeature.c                 | 2 +-
 arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +-
 arch/arm64/mm/context.c                        | 6 +++---
 4 files changed, 8 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index cc70d0ebffa2..842b0cb8c4e2 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -745,11 +745,11 @@ 
 #define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT	16
 #define ID_AA64MMFR0_EL1_SNSMEM_SHIFT		12
 #define ID_AA64MMFR0_EL1_BIGEND_SHIFT		8
-#define ID_AA64MMFR0_EL1_ASID_SHIFT		4
+#define ID_AA64MMFR0_EL1_ASIDBITS_SHIFT		4
 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT		0
 
-#define ID_AA64MMFR0_EL1_ASID_8			0x0
-#define ID_AA64MMFR0_EL1_ASID_16		0x2
+#define ID_AA64MMFR0_EL1_ASIDBITS_8		0x0
+#define ID_AA64MMFR0_EL1_ASIDBITS_16		0x2
 
 #define ID_AA64MMFR0_EL1_TGRAN4_NI		0xf
 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 4c0bc39d1dc3..0d0b599fbfd5 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -352,7 +352,7 @@  static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 	/* Linux shouldn't care about secure memory */
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0),
-	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASID_SHIFT, 4, 0),
+	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0),
 	/*
 	 * Differing PARange is fine as long as all peripherals and memory are mapped
 	 * within the minimum PARange of all CPUs
diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index 0ece26707fc0..0c2e474d0c9e 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -87,7 +87,7 @@ 
  */
 #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\
 	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \
-	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASID), ID_AA64MMFR0_EL1_ASID_16) \
+	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \
 	)
 
 /*
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 8f38a5452d05..e1e0dca01839 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -43,17 +43,17 @@  static u32 get_cpu_asid_bits(void)
 {
 	u32 asid;
 	int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),
-						ID_AA64MMFR0_EL1_ASID_SHIFT);
+						ID_AA64MMFR0_EL1_ASIDBITS_SHIFT);
 
 	switch (fld) {
 	default:
 		pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
 					smp_processor_id(),  fld);
 		fallthrough;
-	case ID_AA64MMFR0_EL1_ASID_8:
+	case ID_AA64MMFR0_EL1_ASIDBITS_8:
 		asid = 8;
 		break;
-	case ID_AA64MMFR0_EL1_ASID_16:
+	case ID_AA64MMFR0_EL1_ASIDBITS_16:
 		asid = 16;
 	}