| Message ID | 20220906135511.144725-9-sergiu.moga@microchip.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Make atmel serial driver aware of GCLK | expand |
On Tue, 6 Sep 2022, Sergiu Moga wrote: > Define the bit that represents the choice of having GCLK as a baudrate > source clock inside the USCLKS bitmask of the Mode Register of > USART IP's. > > Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> > --- > > > v1 -> v2: > - Nothing, this patch was not here before > > > > drivers/tty/serial/atmel_serial.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h > index 0d8a0f9cc5c3..70d0611e56fd 100644 > --- a/drivers/tty/serial/atmel_serial.h > +++ b/drivers/tty/serial/atmel_serial.h > @@ -49,6 +49,7 @@ > #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ > #define ATMEL_US_USCLKS_MCK (0 << 4) > #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) > +#define ATMEL_US_USCLKS_GCLK (2 << 4) This would be FIELD_PREP(ATMEL_US_USCLKS, 2) from linux/bitfield.h. They should all be converted to use FIELD_PREP(), IMHO (in a separate patch). > #define ATMEL_US_USCLKS_SCK (3 << 4) > #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ > #define ATMEL_US_CHRL_5 (0 << 6) >
On 07.09.2022 12:21, Ilpo Järvinen wrote: > On Tue, 6 Sep 2022, Sergiu Moga wrote: > >> Define the bit that represents the choice of having GCLK as a baudrate >> source clock inside the USCLKS bitmask of the Mode Register of >> USART IP's. >> >> Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> >> --- >> >> >> v1 -> v2: >> - Nothing, this patch was not here before >> >> >> >> drivers/tty/serial/atmel_serial.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h >> index 0d8a0f9cc5c3..70d0611e56fd 100644 >> --- a/drivers/tty/serial/atmel_serial.h >> +++ b/drivers/tty/serial/atmel_serial.h >> @@ -49,6 +49,7 @@ >> #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ >> #define ATMEL_US_USCLKS_MCK (0 << 4) >> #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) >> +#define ATMEL_US_USCLKS_GCLK (2 << 4) > > This would be FIELD_PREP(ATMEL_US_USCLKS, 2) from linux/bitfield.h. > > They should all be converted to use FIELD_PREP(), IMHO (in a separate > patch). > >> #define ATMEL_US_USCLKS_SCK (3 << 4) >> #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ >> #define ATMEL_US_CHRL_5 (0 << 6) >> > > -- > i. > Yes, I guess that is a good idea. After these additional macro-definitions are upstreamed, I will try to send some patches for the conversion. Thanks, Sergiu
diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 0d8a0f9cc5c3..70d0611e56fd 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -49,6 +49,7 @@ #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) +#define ATMEL_US_USCLKS_GCLK (2 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ #define ATMEL_US_CHRL_5 (0 << 6)
Define the bit that represents the choice of having GCLK as a baudrate source clock inside the USCLKS bitmask of the Mode Register of USART IP's. Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com> --- v1 -> v2: - Nothing, this patch was not here before drivers/tty/serial/atmel_serial.h | 1 + 1 file changed, 1 insertion(+)