| Message ID | 20221110005507.19464-1-andre.przywara@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: sunxi: H3/H5: Add phys property to USB HCI0 | expand |
Dne četrtek, 10. november 2022 ob 01:55:07 CET je Andre Przywara napisal(a): > As many other Allwinner SoCs from the last years, the first USB host > controller pair in the Allwinner H3 and H5 chips share a USB PHY with > the MUSB OTG controller. This is probably the reason why we didn't have > a "phys" property in those host controller nodes. > This works fine as long as the MUSB controller driver is loaded, as this > takes care of the proper PHY setup, including the muxing between MUSB > and the HCI. > > However this requires the MUSB driver to be enabled and loaded, and also > upsets U-Boot, which cannot use a HCI port without a "phys" property. > > Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: > A64: properly connect USB PHY to port 0"), add the "phys" property to > the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. > > This is not only the proper description of the hardware, but also avoids > a nasty error message in U-Boot triggered by a recent patch. (The port > never worked in host mode, but the error was suppressed due to a bug.) > > When using the MUSB port in OTG mode, this also fixes host mode > switching, so people can use OTG adapters to connect a USB device to > port 0. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com> Best regards, Jernej
Dne četrtek, 10. november 2022 ob 01:55:07 CET je Andre Przywara napisal(a): > As many other Allwinner SoCs from the last years, the first USB host > controller pair in the Allwinner H3 and H5 chips share a USB PHY with > the MUSB OTG controller. This is probably the reason why we didn't have > a "phys" property in those host controller nodes. > This works fine as long as the MUSB controller driver is loaded, as this > takes care of the proper PHY setup, including the muxing between MUSB > and the HCI. > > However this requires the MUSB driver to be enabled and loaded, and also > upsets U-Boot, which cannot use a HCI port without a "phys" property. > > Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: > A64: properly connect USB PHY to port 0"), add the "phys" property to > the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. > > This is not only the proper description of the hardware, but also avoids > a nasty error message in U-Boot triggered by a recent patch. (The port > never worked in host mode, but the error was suppressed due to a bug.) > > When using the MUSB port in OTG mode, this also fixes host mode > switching, so people can use OTG adapters to connect a USB device to > port 0. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> Applied, thanks! Best regards, Jernej
On 11/9/22 18:55, Andre Przywara wrote: > As many other Allwinner SoCs from the last years, the first USB host > controller pair in the Allwinner H3 and H5 chips share a USB PHY with > the MUSB OTG controller. This is probably the reason why we didn't have > a "phys" property in those host controller nodes. > This works fine as long as the MUSB controller driver is loaded, as this > takes care of the proper PHY setup, including the muxing between MUSB > and the HCI. > > However this requires the MUSB driver to be enabled and loaded, and also > upsets U-Boot, which cannot use a HCI port without a "phys" property. > > Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: > A64: properly connect USB PHY to port 0"), add the "phys" property to > the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. > > This is not only the proper description of the hardware, but also avoids > a nasty error message in U-Boot triggered by a recent patch. (The port > never worked in host mode, but the error was suppressed due to a bug.) > > When using the MUSB port in OTG mode, this also fixes host mode > switching, so people can use OTG adapters to connect a USB device to > port 0. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) Reviewed-by: Samuel Holland <samuel@sholland.org> Tested-by: Samuel Holland <samuel@sholland.org>
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 09aefb4e90f8..686193bd6bd9 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -302,6 +302,8 @@ ehci0: usb@1c1a000 { interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; }; @@ -312,6 +314,8 @@ ohci0: usb@1c1a400 { clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>; resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; status = "disabled"; };
As many other Allwinner SoCs from the last years, the first USB host controller pair in the Allwinner H3 and H5 chips share a USB PHY with the MUSB OTG controller. This is probably the reason why we didn't have a "phys" property in those host controller nodes. This works fine as long as the MUSB controller driver is loaded, as this takes care of the proper PHY setup, including the muxing between MUSB and the HCI. However this requires the MUSB driver to be enabled and loaded, and also upsets U-Boot, which cannot use a HCI port without a "phys" property. Similar to what we did in commit cc72570747e4 ("arm64: dts: allwinner: A64: properly connect USB PHY to port 0"), add the "phys" property to the OHCI0 and EHCI0 DT nodes in the shared H3/H5 .dtsi file. This is not only the proper description of the hardware, but also avoids a nasty error message in U-Boot triggered by a recent patch. (The port never worked in host mode, but the error was suppressed due to a bug.) When using the MUSB port in OTG mode, this also fixes host mode switching, so people can use OTG adapters to connect a USB device to port 0. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 4 ++++ 1 file changed, 4 insertions(+)