diff mbox series

[v2,06/26] arm64: Add debug registers affected by HDFGxTR_EL2

Message ID 20230728082952.959212-7-maz@kernel.org (mailing list archive)
State New, archived
Headers show
Series KVM: arm64: NV trap forwarding infrastructure | expand

Commit Message

Marc Zyngier July 28, 2023, 8:29 a.m. UTC 
The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
related registers. Add their encodings (and only that, because
we really don't care about what these registers actually do at
this stage).

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
 1 file changed, 78 insertions(+)

Comments

Catalin Marinas July 28, 2023, 2:14 p.m. UTC | #1 
On Fri, Jul 28, 2023 at 09:29:32AM +0100, Marc Zyngier wrote:
> The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
> related registers. Add their encodings (and only that, because
> we really don't care about what these registers actually do at
> this stage).
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Miguel Luis July 31, 2023, 4:41 p.m. UTC | #2 
Hi Marc,

A few comments on this one, please see below.

> On 28 Jul 2023, at 08:29, Marc Zyngier <maz@kernel.org> wrote:
> 
> The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
> related registers. Add their encodings (and only that, because
> we really don't care about what these registers actually do at
> this stage).
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
> 1 file changed, 78 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 76289339b43b..9dfd127be55a 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -194,6 +194,84 @@
> #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
> #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
> 
> +#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
> +#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
> +#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
> +#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
> +#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
> +#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
> +#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
> +
> +#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
> +#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
> +#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
> +
> +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
> +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)

SYS_TRCITECR_EL1 shows up twice.

> +#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))

Besides m’s restrictions it could be sanitised in op2 to consider only bit m[3].
Suggestion for op2: (2 | ((m & 8) >> 3)))

> +#define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))

Same for SYS_TRCACVR(m) op2: (0 | ((m & 8) >> 3) )

> +#define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
> +#define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
> +#define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
> +#define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
> +#define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
> +#define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
> +#define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
> +#define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
> +#define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
> +#define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
> +#define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
> +#define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
> +#define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
> +#define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
> +#define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
> +#define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
> +#define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
> +#define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
> +#define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
> +#define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
> +#define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
> +#define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
> +#define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
> +#define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
> +#define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
> +#define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
> +#define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
> +#define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
> +#define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
> +#define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
> +#define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
> +#define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
> +#define SYS_TRCIMSPEC0 sys_reg(2, 1, 0, 0, 7)
> +#define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)

Since ‘m' restrictions are not being considered, when m = 0 it clashes with
SYS_TRCIMSPEC0 so overall SYS_TRCIMSPEC(m) already covers
SYS_TRCIMSPEC0. Is this redundancy needed?

> +#define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
> +#define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
> +#define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
> +#define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
> +#define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))

Suggestion for SYS_TRCRSCTLR(m) op2: (0 | ((m & 16) >> 4))

> +#define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
> +#define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)

Without considering ‘m' restrictions CRm can clash with 3.

Please let me know if I missed something.

Thanks
Miguel

> +#define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
> +#define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
> +#define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
> +#define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
> +#define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
> +#define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
> +#define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
> +#define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
> +#define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
> +#define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
> +#define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
> +#define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
> +#define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
> +#define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
> +#define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
> +#define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
> +#define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
> +
> +/* ETM */
> +#define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
> +
> #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
> #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
> #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
> -- 
> 2.34.1
>
Marc Zyngier Aug. 2, 2023, 5:52 p.m. UTC | #3 
On Mon, 31 Jul 2023 17:41:41 +0100,
Miguel Luis <miguel.luis@oracle.com> wrote:
> 
> Hi Marc,
> 
> A few comments on this one, please see below.
> 
> > On 28 Jul 2023, at 08:29, Marc Zyngier <maz@kernel.org> wrote:
> > 
> > The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
> > related registers. Add their encodings (and only that, because
> > we really don't care about what these registers actually do at
> > this stage).
> > 
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> > arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
> > 1 file changed, 78 insertions(+)
> > 
> > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> > index 76289339b43b..9dfd127be55a 100644
> > --- a/arch/arm64/include/asm/sysreg.h
> > +++ b/arch/arm64/include/asm/sysreg.h
> > @@ -194,6 +194,84 @@
> > #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
> > #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
> > 
> > +#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
> > +#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
> > +#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
> > +#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
> > +#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
> > +#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
> > +#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
> > +
> > +#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
> > +#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
> > +#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
> > +
> > +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
> > +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
> 
> SYS_TRCITECR_EL1 shows up twice.

Ah, nice one. Too many registers.

> 
> > +#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
> 
> Besides m’s restrictions it could be sanitised in op2 to consider only bit m[3].
> Suggestion for op2: (2 | ((m & 8) >> 3)))

It is fully expected that 'm' will be in the 0-15 range, as per the
architecture (D19.4.8), and the tables only use that exact range.

Do you see an actual bug, or is this defensive programming?

Thanks,

	M.
Miguel Luis Aug. 3, 2023, midnight UTC | #4 
Hi Marc,

> On 2 Aug 2023, at 17:52, Marc Zyngier <maz@kernel.org> wrote:
> 
> On Mon, 31 Jul 2023 17:41:41 +0100,
> Miguel Luis <miguel.luis@oracle.com> wrote:
>> 
>> Hi Marc,
>> 
>> A few comments on this one, please see below.
>> 
>>> On 28 Jul 2023, at 08:29, Marc Zyngier <maz@kernel.org> wrote:
>>> 
>>> The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
>>> related registers. Add their encodings (and only that, because
>>> we really don't care about what these registers actually do at
>>> this stage).
>>> 
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>> ---
>>> arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
>>> 1 file changed, 78 insertions(+)
>>> 
>>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>>> index 76289339b43b..9dfd127be55a 100644
>>> --- a/arch/arm64/include/asm/sysreg.h
>>> +++ b/arch/arm64/include/asm/sysreg.h
>>> @@ -194,6 +194,84 @@
>>> #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
>>> #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
>>> 
>>> +#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
>>> +#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
>>> +#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
>>> +#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
>>> +#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
>>> +#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
>>> +#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
>>> +
>>> +#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
>>> +#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
>>> +#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
>>> +
>>> +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
>>> +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
>> 
>> SYS_TRCITECR_EL1 shows up twice.
> 
> Ah, nice one. Too many registers.
> 
>> 
>>> +#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
>> 
>> Besides m’s restrictions it could be sanitised in op2 to consider only bit m[3].
>> Suggestion for op2: (2 | ((m & 8) >> 3)))
> 
> It is fully expected that 'm' will be in the 0-15 range, as per the
> architecture (D19.4.8), and the tables only use that exact range.
> 
> Do you see an actual bug, or is this defensive programming?
> 

I was seeing a problem when m[5]=1 then Op2 of 0b01:m[3] isn’t guaranteed
anymore overridden with 0b11:m[3].

Clearly ‘m’ would be outside the range but not messing with Op2 fixed bits 0b01.
Not a problem for patch 21 though.

Due to the uncertainty if this can bite later, hence the suggestion and also
open to advices.

Thank you,

Miguel


> Thanks,
> 
> M.
> 
> -- 
> Without deviation from the norm, progress is not possible.
Marc Zyngier Aug. 7, 2023, 12:40 p.m. UTC | #5 
On Thu, 03 Aug 2023 01:00:52 +0100,
Miguel Luis <miguel.luis@oracle.com> wrote:
> 
> Hi Marc,
> 
> > On 2 Aug 2023, at 17:52, Marc Zyngier <maz@kernel.org> wrote:
> > 
> > On Mon, 31 Jul 2023 17:41:41 +0100,
> > Miguel Luis <miguel.luis@oracle.com> wrote:
> >> 
> >> Hi Marc,
> >> 
> >> A few comments on this one, please see below.
> >> 
> >>> On 28 Jul 2023, at 08:29, Marc Zyngier <maz@kernel.org> wrote:
> >>> 
> >>> The HDFGxTR_EL2 registers trap a (huge) set of debug and trace
> >>> related registers. Add their encodings (and only that, because
> >>> we really don't care about what these registers actually do at
> >>> this stage).
> >>> 
> >>> Signed-off-by: Marc Zyngier <maz@kernel.org>
> >>> ---
> >>> arch/arm64/include/asm/sysreg.h | 78 +++++++++++++++++++++++++++++++++
> >>> 1 file changed, 78 insertions(+)
> >>> 
> >>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> >>> index 76289339b43b..9dfd127be55a 100644
> >>> --- a/arch/arm64/include/asm/sysreg.h
> >>> +++ b/arch/arm64/include/asm/sysreg.h
> >>> @@ -194,6 +194,84 @@
> >>> #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
> >>> #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
> >>> 
> >>> +#define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
> >>> +#define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
> >>> +#define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
> >>> +#define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1)
> >>> +#define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
> >>> +#define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2)
> >>> +#define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
> >>> +
> >>> +#define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
> >>> +#define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
> >>> +#define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
> >>> +
> >>> +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
> >>> +#define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
> >> 
> >> SYS_TRCITECR_EL1 shows up twice.
> > 
> > Ah, nice one. Too many registers.
> > 
> >> 
> >>> +#define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
> >> 
> >> Besides m’s restrictions it could be sanitised in op2 to consider only bit m[3].
> >> Suggestion for op2: (2 | ((m & 8) >> 3)))
> > 
> > It is fully expected that 'm' will be in the 0-15 range, as per the
> > architecture (D19.4.8), and the tables only use that exact range.
> > 
> > Do you see an actual bug, or is this defensive programming?
> > 
> 
> I was seeing a problem when m[5]=1 then Op2 of 0b01:m[3] isn’t guaranteed
> anymore overridden with 0b11:m[3].

But that'd be wrong anyway. Now, we'd have an encoding that possibly
aliases to something else, and we don't know about it.

> Clearly ‘m’ would be outside the range but not messing with Op2 fixed bits 0b01.
> Not a problem for patch 21 though.

All these macros have as the basis for their use that you use *valid*
input.

> Due to the uncertainty if this can bite later, hence the suggestion and also
> open to advices.

If you really want some defensive programming on that front, then you
should make sure we detect the issue at compile time, rather than
silently changing the encoding.

Thanks,

	M.
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 76289339b43b..9dfd127be55a 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -194,6 +194,84 @@ 
 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
 
+#define SYS_BRBINF_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
+#define SYS_BRBINFINJ_EL1		sys_reg(2, 1, 9, 1, 0)
+#define SYS_BRBSRC_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1))
+#define SYS_BRBSRCINJ_EL1		sys_reg(2, 1, 9, 1, 1)
+#define SYS_BRBTGT_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2))
+#define SYS_BRBTGTINJ_EL1		sys_reg(2, 1, 9, 1, 2)
+#define SYS_BRBTS_EL1			sys_reg(2, 1, 9, 0, 2)
+
+#define SYS_BRBCR_EL1			sys_reg(2, 1, 9, 0, 0)
+#define SYS_BRBFCR_EL1			sys_reg(2, 1, 9, 0, 1)
+#define SYS_BRBIDR0_EL1			sys_reg(2, 1, 9, 2, 0)
+
+#define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
+#define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
+#define SYS_TRCACATR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
+#define SYS_TRCACVR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
+#define SYS_TRCAUTHSTATUS		sys_reg(2, 1, 7, 14, 6)
+#define SYS_TRCAUXCTLR			sys_reg(2, 1, 0, 6, 0)
+#define SYS_TRCBBCTLR			sys_reg(2, 1, 0, 15, 0)
+#define SYS_TRCCCCTLR			sys_reg(2, 1, 0, 14, 0)
+#define SYS_TRCCIDCCTLR0		sys_reg(2, 1, 3, 0, 2)
+#define SYS_TRCCIDCCTLR1		sys_reg(2, 1, 3, 1, 2)
+#define SYS_TRCCIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 0)
+#define SYS_TRCCLAIMCLR			sys_reg(2, 1, 7, 9, 6)
+#define SYS_TRCCLAIMSET			sys_reg(2, 1, 7, 8, 6)
+#define SYS_TRCCNTCTLR(m)		sys_reg(2, 1, 0, (4 | (m & 3)), 5)
+#define SYS_TRCCNTRLDVR(m)		sys_reg(2, 1, 0, (0 | (m & 3)), 5)
+#define SYS_TRCCNTVR(m)			sys_reg(2, 1, 0, (8 | (m & 3)), 5)
+#define SYS_TRCCONFIGR			sys_reg(2, 1, 0, 4, 0)
+#define SYS_TRCDEVARCH			sys_reg(2, 1, 7, 15, 6)
+#define SYS_TRCDEVID			sys_reg(2, 1, 7, 2, 7)
+#define SYS_TRCEVENTCTL0R		sys_reg(2, 1, 0, 8, 0)
+#define SYS_TRCEVENTCTL1R		sys_reg(2, 1, 0, 9, 0)
+#define SYS_TRCEXTINSELR(m)		sys_reg(2, 1, 0, (8 | (m & 3)), 4)
+#define SYS_TRCIDR0			sys_reg(2, 1, 0, 8, 7)
+#define SYS_TRCIDR10			sys_reg(2, 1, 0, 2, 6)
+#define SYS_TRCIDR11			sys_reg(2, 1, 0, 3, 6)
+#define SYS_TRCIDR12			sys_reg(2, 1, 0, 4, 6)
+#define SYS_TRCIDR13			sys_reg(2, 1, 0, 5, 6)
+#define SYS_TRCIDR1			sys_reg(2, 1, 0, 9, 7)
+#define SYS_TRCIDR2			sys_reg(2, 1, 0, 10, 7)
+#define SYS_TRCIDR3			sys_reg(2, 1, 0, 11, 7)
+#define SYS_TRCIDR4			sys_reg(2, 1, 0, 12, 7)
+#define SYS_TRCIDR5			sys_reg(2, 1, 0, 13, 7)
+#define SYS_TRCIDR6			sys_reg(2, 1, 0, 14, 7)
+#define SYS_TRCIDR7			sys_reg(2, 1, 0, 15, 7)
+#define SYS_TRCIDR8			sys_reg(2, 1, 0, 0, 6)
+#define SYS_TRCIDR9			sys_reg(2, 1, 0, 1, 6)
+#define SYS_TRCIMSPEC0			sys_reg(2, 1, 0, 0, 7)
+#define SYS_TRCIMSPEC(m)		sys_reg(2, 1, 0, (m & 7), 7)
+#define SYS_TRCITEEDCR			sys_reg(2, 1, 0, 2, 1)
+#define SYS_TRCOSLSR			sys_reg(2, 1, 1, 1, 4)
+#define SYS_TRCPRGCTLR			sys_reg(2, 1, 0, 1, 0)
+#define SYS_TRCQCTLR			sys_reg(2, 1, 0, 1, 1)
+#define SYS_TRCRSCTLR(m)		sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
+#define SYS_TRCRSR			sys_reg(2, 1, 0, 10, 0)
+#define SYS_TRCSEQEVR(m)		sys_reg(2, 1, 0, (m & 3), 4)
+#define SYS_TRCSEQRSTEVR		sys_reg(2, 1, 0, 6, 4)
+#define SYS_TRCSEQSTR			sys_reg(2, 1, 0, 7, 4)
+#define SYS_TRCSSCCR(m)			sys_reg(2, 1, 1, (m & 7), 2)
+#define SYS_TRCSSCSR(m)			sys_reg(2, 1, 1, (8 | (m & 7)), 2)
+#define SYS_TRCSSPCICR(m)		sys_reg(2, 1, 1, (m & 7), 3)
+#define SYS_TRCSTALLCTLR		sys_reg(2, 1, 0, 11, 0)
+#define SYS_TRCSTATR			sys_reg(2, 1, 0, 3, 0)
+#define SYS_TRCSYNCPR			sys_reg(2, 1, 0, 13, 0)
+#define SYS_TRCTRACEIDR			sys_reg(2, 1, 0, 0, 1)
+#define SYS_TRCTSCTLR			sys_reg(2, 1, 0, 12, 0)
+#define SYS_TRCVICTLR			sys_reg(2, 1, 0, 0, 2)
+#define SYS_TRCVIIECTLR			sys_reg(2, 1, 0, 1, 2)
+#define SYS_TRCVIPCSSCTLR		sys_reg(2, 1, 0, 3, 2)
+#define SYS_TRCVISSCTLR			sys_reg(2, 1, 0, 2, 2)
+#define SYS_TRCVMIDCCTLR0		sys_reg(2, 1, 3, 2, 2)
+#define SYS_TRCVMIDCCTLR1		sys_reg(2, 1, 3, 3, 2)
+#define SYS_TRCVMIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 1)
+
+/* ETM */
+#define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)
+
 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)