| Message ID | 20231018061714.3553817-8-s.hauer@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add perf support to the rockchip-dfi driver | expand |
On 23. 10. 18. 15:16, Sascha Hauer wrote: > Different Rockchip SoC variants have a different number of channels. > Introduce a channel mask to make the number of channels configurable > from SoC initialization code. > > Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > --- > > Notes: > Changes since v7: > - Loop only over channels present on a SoC > > drivers/devfreq/event/rockchip-dfi.c | 25 +++++++++++++++++++------ > 1 file changed, 19 insertions(+), 6 deletions(-) > > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > index 126bb744645b6..28c18bbf6baa5 100644 > --- a/drivers/devfreq/event/rockchip-dfi.c > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -18,10 +18,11 @@ > #include <linux/list.h> > #include <linux/of.h> > #include <linux/of_device.h> > +#include <linux/bits.h> > > #include <soc/rockchip/rk3399_grf.h> > > -#define RK3399_DMC_NUM_CH 2 > +#define DMC_MAX_CHANNELS 2 > > /* DDRMON_CTRL */ > #define DDRMON_CTRL 0x04 > @@ -44,7 +45,7 @@ struct dmc_count_channel { > }; > > struct dmc_count { > - struct dmc_count_channel c[RK3399_DMC_NUM_CH]; > + struct dmc_count_channel c[DMC_MAX_CHANNELS]; > }; > > /* > @@ -61,6 +62,8 @@ struct rockchip_dfi { > struct regmap *regmap_pmu; > struct clk *clk; > u32 ddr_type; > + unsigned int channel_mask; > + unsigned int max_channels; > }; > > static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) > @@ -95,7 +98,9 @@ static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm > u32 i; > void __iomem *dfi_regs = dfi->regs; > > - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { > + for (i = 0; i < dfi->max_channels; i++) { > + if (!(dfi->channel_mask & BIT(i))) > + continue; > count->c[i].access = readl_relaxed(dfi_regs + > DDRMON_CH0_DFI_ACCESS_NUM + i * 20); > count->c[i].total = readl_relaxed(dfi_regs + > @@ -145,9 +150,14 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, > rockchip_dfi_read_counters(edev, &count); > > /* We can only report one channel, so find the busiest one */ > - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { > - u32 a = count.c[i].access - last->c[i].access; > - u32 t = count.c[i].total - last->c[i].total; > + for (i = 0; i < dfi->max_channels; i++) { > + u32 a, t; > + > + if (!(dfi->channel_mask & BIT(i))) > + continue; > + > + a = count.c[i].access - last->c[i].access; > + t = count.c[i].total - last->c[i].total; > > if (a > access) { > access = a; > @@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) > dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & > RK3399_PMUGRF_DDRTYPE_MASK; > > + dfi->channel_mask = GENMASK(1, 0); > + dfi->max_channels = 2; > + > return 0; > }; > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> -----Original Message----- > From: Chanwoo Choi <chanwoo@kernel.org> > Sent: Thursday, October 19, 2023 12:06 AM > To: Sascha Hauer <s.hauer@pengutronix.de>; linux- > rockchip@lists.infradead.org > Cc: linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > linux-pm@vger.kernel.org; Heiko Stuebner <heiko@sntech.de>; Kyungmin Park > <kyungmin.park@samsung.com>; MyungJoo Ham <myungjoo.ham@samsung.com>; Will > Deacon <will@kernel.org>; Mark Rutland <mark.rutland@arm.com>; > kernel@pengutronix.de; Michael Riesch <michael.riesch@wolfvision.net>; > Robin Murphy <robin.murphy@arm.com>; Vincent Legoll > <vincent.legoll@gmail.com>; Rob Herring <robh+dt@kernel.org>; Krzysztof > Kozlowski <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley > <conor+dt@kernel.org>; devicetree@vger.kernel.org; Sebastian Reichel > <sebastian.reichel@collabora.com> > Subject: Re: [PATCH v8 07/26] PM / devfreq: rockchip-dfi: introduce > channel mask > > On 23. 10. 18. 15:16, Sascha Hauer wrote: > > Different Rockchip SoC variants have a different number of channels. > > Introduce a channel mask to make the number of channels configurable > > from SoC initialization code. > > > > Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> > > --- > > > > Notes: > > Changes since v7: > > - Loop only over channels present on a SoC > > > > drivers/devfreq/event/rockchip-dfi.c | 25 +++++++++++++++++++------ > > 1 file changed, 19 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/devfreq/event/rockchip-dfi.c > > b/drivers/devfreq/event/rockchip-dfi.c > > index 126bb744645b6..28c18bbf6baa5 100644 > > --- a/drivers/devfreq/event/rockchip-dfi.c > > +++ b/drivers/devfreq/event/rockchip-dfi.c > > @@ -18,10 +18,11 @@ > > #include <linux/list.h> > > #include <linux/of.h> > > #include <linux/of_device.h> > > +#include <linux/bits.h> > > > > #include <soc/rockchip/rk3399_grf.h> > > > > -#define RK3399_DMC_NUM_CH 2 > > +#define DMC_MAX_CHANNELS 2 > > > > /* DDRMON_CTRL */ > > #define DDRMON_CTRL 0x04 > > @@ -44,7 +45,7 @@ struct dmc_count_channel { }; > > > > struct dmc_count { > > - struct dmc_count_channel c[RK3399_DMC_NUM_CH]; > > + struct dmc_count_channel c[DMC_MAX_CHANNELS]; > > }; > > > > /* > > @@ -61,6 +62,8 @@ struct rockchip_dfi { > > struct regmap *regmap_pmu; > > struct clk *clk; > > u32 ddr_type; > > + unsigned int channel_mask; > > + unsigned int max_channels; > > }; > > > > static void rockchip_dfi_start_hardware_counter(struct > > devfreq_event_dev *edev) @@ -95,7 +98,9 @@ static void > rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm > > u32 i; > > void __iomem *dfi_regs = dfi->regs; > > > > - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { > > + for (i = 0; i < dfi->max_channels; i++) { > > + if (!(dfi->channel_mask & BIT(i))) > > + continue; > > count->c[i].access = readl_relaxed(dfi_regs + > > DDRMON_CH0_DFI_ACCESS_NUM + i * 20); > > count->c[i].total = readl_relaxed(dfi_regs + @@ -145,9 > +150,14 @@ > > static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, > > rockchip_dfi_read_counters(edev, &count); > > > > /* We can only report one channel, so find the busiest one */ > > - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { > > - u32 a = count.c[i].access - last->c[i].access; > > - u32 t = count.c[i].total - last->c[i].total; > > + for (i = 0; i < dfi->max_channels; i++) { > > + u32 a, t; > > + > > + if (!(dfi->channel_mask & BIT(i))) > > + continue; > > + > > + a = count.c[i].access - last->c[i].access; > > + t = count.c[i].total - last->c[i].total; > > > > if (a > access) { > > access = a; > > @@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) > > dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & > > RK3399_PMUGRF_DDRTYPE_MASK; > > > > + dfi->channel_mask = GENMASK(1, 0); > > + dfi->max_channels = 2; > > + > > return 0; > > }; > > > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com> > Applied it. Thanks. Best Regards, Chanwoo Choi
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 126bb744645b6..28c18bbf6baa5 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -18,10 +18,11 @@ #include <linux/list.h> #include <linux/of.h> #include <linux/of_device.h> +#include <linux/bits.h> #include <soc/rockchip/rk3399_grf.h> -#define RK3399_DMC_NUM_CH 2 +#define DMC_MAX_CHANNELS 2 /* DDRMON_CTRL */ #define DDRMON_CTRL 0x04 @@ -44,7 +45,7 @@ struct dmc_count_channel { }; struct dmc_count { - struct dmc_count_channel c[RK3399_DMC_NUM_CH]; + struct dmc_count_channel c[DMC_MAX_CHANNELS]; }; /* @@ -61,6 +62,8 @@ struct rockchip_dfi { struct regmap *regmap_pmu; struct clk *clk; u32 ddr_type; + unsigned int channel_mask; + unsigned int max_channels; }; static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) @@ -95,7 +98,9 @@ static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dm u32 i; void __iomem *dfi_regs = dfi->regs; - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { + for (i = 0; i < dfi->max_channels; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; count->c[i].access = readl_relaxed(dfi_regs + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); count->c[i].total = readl_relaxed(dfi_regs + @@ -145,9 +150,14 @@ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, rockchip_dfi_read_counters(edev, &count); /* We can only report one channel, so find the busiest one */ - for (i = 0; i < RK3399_DMC_NUM_CH; i++) { - u32 a = count.c[i].access - last->c[i].access; - u32 t = count.c[i].total - last->c[i].total; + for (i = 0; i < dfi->max_channels; i++) { + u32 a, t; + + if (!(dfi->channel_mask & BIT(i))) + continue; + + a = count.c[i].access - last->c[i].access; + t = count.c[i].total - last->c[i].total; if (a > access) { access = a; @@ -185,6 +195,9 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & RK3399_PMUGRF_DDRTYPE_MASK; + dfi->channel_mask = GENMASK(1, 0); + dfi->max_channels = 2; + return 0; };