diff mbox series

[v2,03/12] KVM: arm64: Add latest HFGITR_EL2 FGT entries to nested virt

Message ID 20231206100503.564090-4-tabba@google.com (mailing list archive)
State New, archived
Headers show
Series KVM: arm64: Fixes to fine grain traps and pKVM traps | expand

Commit Message

Fuad Tabba Dec. 6, 2023, 10:04 a.m. UTC
Add the missing nested virt FGT table entries HFGITR_EL2. Based
on the 2023-09 Arm Architecture System Registers xml
specification [*]. Add the missing field definitions as well,
both to generate the correct RES0 mask and to be able to toggle
their FGT bits.

Also adds definitions of some of the missing system registers and
instructions, which can be trapped by the FGT bits.

[*] https://developer.arm.com/downloads/-/exploration-tools

Signed-off-by: Fuad Tabba <tabba@google.com>
---
 arch/arm64/include/asm/sysreg.h | 7 +++++++
 arch/arm64/kvm/emulate-nested.c | 5 +++++
 arch/arm64/tools/sysreg         | 4 +++-
 3 files changed, 15 insertions(+), 1 deletion(-)

Comments

Mark Brown Dec. 7, 2023, 5:14 p.m. UTC | #1
On Wed, Dec 06, 2023 at 10:04:53AM +0000, Fuad Tabba wrote:

> Add the missing nested virt FGT table entries HFGITR_EL2. Based
> on the 2023-09 Arm Architecture System Registers xml
> specification [*]. Add the missing field definitions as well,
> both to generate the correct RES0 mask and to be able to toggle
> their FGT bits.
> 
> Also adds definitions of some of the missing system registers and
> instructions, which can be trapped by the FGT bits.
> 
> [*] https://developer.arm.com/downloads/-/exploration-tools

That should be a reference to DDI0602 (for the instruction XML) and
DD0601 (for the system register XML) - it's the same content, just a
more stable name.

>  Sysreg HFGITR_EL2	3	4	1	1	6
> -Res0	63:61
> +Res0	63
> +Field	62	ATS1E1A
> +Res0	61
>  Field	60	COSPRCTX
>  Field	59	nGCSEPP
>  Field	58	nGCSSTR_EL1

The sysreg looks good:

Reviewed-by: Mark Brown <broonie@kernel.org>
Fuad Tabba Dec. 8, 2023, 8:17 a.m. UTC | #2
Hi Mark,

On Thu, Dec 7, 2023 at 5:14 PM Mark Brown <broonie@kernel.org> wrote:
>
> On Wed, Dec 06, 2023 at 10:04:53AM +0000, Fuad Tabba wrote:
>
> > Add the missing nested virt FGT table entries HFGITR_EL2. Based
> > on the 2023-09 Arm Architecture System Registers xml
> > specification [*]. Add the missing field definitions as well,
> > both to generate the correct RES0 mask and to be able to toggle
> > their FGT bits.
> >
> > Also adds definitions of some of the missing system registers and
> > instructions, which can be trapped by the FGT bits.
> >
> > [*] https://developer.arm.com/downloads/-/exploration-tools
>
> That should be a reference to DDI0602 (for the instruction XML) and
> DD0601 (for the system register XML) - it's the same content, just a
> more stable name.

Got it. Will fix it on the respin.

Cheers,
/fuad

>
> >  Sysreg HFGITR_EL2    3       4       1       1       6
> > -Res0 63:61
> > +Res0 63
> > +Field        62      ATS1E1A
> > +Res0 61
> >  Field        60      COSPRCTX
> >  Field        59      nGCSEPP
> >  Field        58      nGCSSTR_EL1
>
> The sysreg looks good:
>
> Reviewed-by: Mark Brown <broonie@kernel.org>
diff mbox series

Patch

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 7b469b3ac1f9..5892f9f1b541 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -658,6 +658,7 @@ 
 #define OP_AT_S1E0W	sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
 #define OP_AT_S1E1RP	sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
 #define OP_AT_S1E1WP	sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
+#define OP_AT_S1E1A	sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
 #define OP_AT_S1E2R	sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
 #define OP_AT_S1E2W	sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
 #define OP_AT_S12E1R	sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
@@ -794,10 +795,16 @@ 
 #define OP_TLBI_VMALLS12E1NXS		sys_insn(1, 4, 9, 7, 6)
 
 /* Misc instructions */
+#define OP_GCSPUSHX			sys_insn(1, 0, 7, 7, 4)
+#define OP_GCSPOPCX			sys_insn(1, 0, 7, 7, 5)
+#define OP_GCSPOPX			sys_insn(1, 0, 7, 7, 6)
+#define OP_GCSPUSHM			sys_insn(1, 3, 7, 7, 0)
+
 #define OP_BRB_IALL			sys_insn(1, 1, 7, 2, 4)
 #define OP_BRB_INJ			sys_insn(1, 1, 7, 2, 5)
 #define OP_CFP_RCTX			sys_insn(1, 3, 7, 3, 4)
 #define OP_DVP_RCTX			sys_insn(1, 3, 7, 3, 5)
+#define OP_COSP_RCTX			sys_insn(1, 3, 7, 3, 6)
 #define OP_CPP_RCTX			sys_insn(1, 3, 7, 3, 7)
 
 /* Common SCTLR_ELx flags. */
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 8b473a1bbc11..89901550db34 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -1117,6 +1117,11 @@  static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
 	SR_FGT(SYS_AFSR1_EL1, 		HFGxTR, AFSR1_EL1, 1),
 	SR_FGT(SYS_AFSR0_EL1, 		HFGxTR, AFSR0_EL1, 1),
 	/* HFGITR_EL2 */
+	SR_FGT(OP_AT_S1E1A, 		HFGITR, ATS1E1A, 1),
+	SR_FGT(OP_COSP_RCTX, 		HFGITR, COSPRCTX, 1),
+	SR_FGT(OP_GCSPUSHX, 		HFGITR, nGCSEPP, 0),
+	SR_FGT(OP_GCSPOPX, 		HFGITR, nGCSEPP, 0),
+	SR_FGT(OP_GCSPUSHM, 		HFGITR, nGCSPUSHM_EL1, 0),
 	SR_FGT(OP_BRB_IALL, 		HFGITR, nBRBIALL, 0),
 	SR_FGT(OP_BRB_INJ, 		HFGITR, nBRBINJ, 0),
 	SR_FGT(SYS_DC_CVAC, 		HFGITR, DCCVAC, 1),
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c6cc8f2396e6..61cc3bcfc3fa 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2102,7 +2102,9 @@  Fields	HFGxTR_EL2
 EndSysreg
 
 Sysreg HFGITR_EL2	3	4	1	1	6
-Res0	63:61
+Res0	63
+Field	62	ATS1E1A
+Res0	61
 Field	60	COSPRCTX
 Field	59	nGCSEPP
 Field	58	nGCSSTR_EL1