| Message ID | 20240415-dev-charlie-support_thead_vector_6_9-v2-4-c7d68c603268@rivosinc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | riscv: Support vendor extensions and xtheadvector | expand |
On Mon, Apr 15, 2024 at 09:12:01PM -0700, Charlie Jenkins wrote: > The D1/D1s SoCs support xtheadvector which should be included in the > devicetree. Also include vendorid for the cpu. > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > --- > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > index 64c3c2e6cbe0..4788bb50afa2 100644 > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > riscv,isa = "rv64imafdc"; > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > - "zifencei", "zihpm"; > + "zifencei", "zihpm", "xtheadvector"; > + riscv,vendorid = <0x00000000 0x0000005b7>; Isn't this effectively useless given there's only one CPU here? We also already know the vendor of the hart, because the compatible says it is a "thead,c906" so this doesn't provide any new information. > #cooling-cells = <2>; > > cpu0_intc: interrupt-controller { > > -- > 2.44.0 >
On Tue, Apr 16, 2024 at 04:28:19PM +0100, Conor Dooley wrote: > On Mon, Apr 15, 2024 at 09:12:01PM -0700, Charlie Jenkins wrote: > > The D1/D1s SoCs support xtheadvector which should be included in the > > devicetree. Also include vendorid for the cpu. > > > > Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> > > --- > > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > index 64c3c2e6cbe0..4788bb50afa2 100644 > > --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > > @@ -27,7 +27,8 @@ cpu0: cpu@0 { > > riscv,isa = "rv64imafdc"; > > riscv,isa-base = "rv64i"; > > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > > - "zifencei", "zihpm"; > > + "zifencei", "zihpm", "xtheadvector"; > > > > + riscv,vendorid = <0x00000000 0x0000005b7>; > > Isn't this effectively useless given there's only one CPU here? > We also already know the vendor of the hart, because the compatible says > it is a "thead,c906" so this doesn't provide any new information. Yes, it was simply to provide an example of using this field to make it easier for somebody who wants to use it in the future. I can remove it if it's confusing. - Charlie > > > #cooling-cells = <2>; > > > > cpu0_intc: interrupt-controller { > > > > -- > > 2.44.0 > >
diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..4788bb50afa2 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,8 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadvector"; + riscv,vendorid = <0x00000000 0x0000005b7>; #cooling-cells = <2>; cpu0_intc: interrupt-controller {
The D1/D1s SoCs support xtheadvector which should be included in the devicetree. Also include vendorid for the cpu. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)