Message ID | 20240415-dev-charlie-support_thead_vector_6_9-v2-9-c7d68c603268@rivosinc.com (mailing list archive) |
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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org |
Series |
riscv: Support vendor extensions and xtheadvector
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expand
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diff --git a/arch/riscv/lib/uaccess.S b/arch/riscv/lib/uaccess.S index bc22c078aba8..1fe798666aee 100644 --- a/arch/riscv/lib/uaccess.S +++ b/arch/riscv/lib/uaccess.S @@ -5,6 +5,7 @@ #include <asm/csr.h> #include <asm/hwcap.h> #include <asm/alternative-macros.h> +#include <asm/vendorid_list.h> .macro fixup op reg addr lbl 100: @@ -15,6 +16,7 @@ SYM_FUNC_START(__asm_copy_to_user) #ifdef CONFIG_RISCV_ISA_V ALTERNATIVE("j fallback_scalar_usercopy", "nop", 0, RISCV_ISA_EXT_v, CONFIG_RISCV_ISA_V) + ALTERNATIVE("nop", "j fallback_scalar_usercopy", THEAD_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, CONFIG_RISCV_ISA_XTHEADVECTOR) REG_L t0, riscv_v_usercopy_threshold bltu a2, t0, fallback_scalar_usercopy tail enter_vector_usercopy
At this time, use the fallback uaccess routines rather than customizing the vectorized uaccess routines to be compatible with xtheadvector. Signed-off-by: Charlie Jenkins <charlie@rivosinc.com> --- arch/riscv/lib/uaccess.S | 2 ++ 1 file changed, 2 insertions(+)