Message ID | 43702e492090417a490ba4cd81990a05aeea9f48.1598621459.git.cristian.ciocaltea@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add initial support for RoseapplePi SBC | expand |
On 0828, Cristian Ciocaltea wrote: > The PPI interrupts for cortex-a9 were incorrectly specified, fix them. > > Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar") > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > Reviewed-by: Peter Korsgaard <peter@korsgaard.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > arch/arm/boot/dts/owl-s500.dtsi | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi > index 5ceb6cc4451d..1dbe4e8b38ac 100644 > --- a/arch/arm/boot/dts/owl-s500.dtsi > +++ b/arch/arm/boot/dts/owl-s500.dtsi > @@ -84,21 +84,21 @@ scu: scu@b0020000 { > global_timer: timer@b0020200 { > compatible = "arm,cortex-a9-global-timer"; > reg = <0xb0020200 0x100>; > - interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > status = "disabled"; > }; > > twd_timer: timer@b0020600 { > compatible = "arm,cortex-a9-twd-timer"; > reg = <0xb0020600 0x20>; > - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > status = "disabled"; > }; > > twd_wdt: wdt@b0020620 { > compatible = "arm,cortex-a9-twd-wdt"; > reg = <0xb0020620 0xe0>; > - interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > status = "disabled"; > }; > > -- > 2.28.0 >
On Mon, Aug 31, 2020 at 02:49:25PM +0530, Manivannan Sadhasivam wrote: > On 0828, Cristian Ciocaltea wrote: > > The PPI interrupts for cortex-a9 were incorrectly specified, fix them. > > > > Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar") > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com> > > Reviewed-by: Peter Korsgaard <peter@korsgaard.com> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Cristi > Thanks, > Mani > > > --- > > arch/arm/boot/dts/owl-s500.dtsi | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi > > index 5ceb6cc4451d..1dbe4e8b38ac 100644 > > --- a/arch/arm/boot/dts/owl-s500.dtsi > > +++ b/arch/arm/boot/dts/owl-s500.dtsi > > @@ -84,21 +84,21 @@ scu: scu@b0020000 { > > global_timer: timer@b0020200 { > > compatible = "arm,cortex-a9-global-timer"; > > reg = <0xb0020200 0x100>; > > - interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > > + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > > status = "disabled"; > > }; > > > > twd_timer: timer@b0020600 { > > compatible = "arm,cortex-a9-twd-timer"; > > reg = <0xb0020600 0x20>; > > - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > > status = "disabled"; > > }; > > > > twd_wdt: wdt@b0020620 { > > compatible = "arm,cortex-a9-twd-wdt"; > > reg = <0xb0020620 0xe0>; > > - interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > > + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; > > status = "disabled"; > > }; > > > > -- > > 2.28.0 > >
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi index 5ceb6cc4451d..1dbe4e8b38ac 100644 --- a/arch/arm/boot/dts/owl-s500.dtsi +++ b/arch/arm/boot/dts/owl-s500.dtsi @@ -84,21 +84,21 @@ scu: scu@b0020000 { global_timer: timer@b0020200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xb0020200 0x100>; - interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; status = "disabled"; }; twd_timer: timer@b0020600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xb0020600 0x20>; - interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; status = "disabled"; }; twd_wdt: wdt@b0020620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0xb0020620 0xe0>; - interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; status = "disabled"; };