| Message ID | c2f8d42a5bd8e1b6acc38d6c24eee4dcb9948bfd.1715332922.git.andrea.porta@suse.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add minimal boot support for Raspberry Pi 5 | expand |
Hi Andrea, Am 10.05.24 um 16:35 schrieb Andrea della Porta: > Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG > register block present on other STB chips. Add support for BCM2712 > SD capabilities of this chipset. > The silicon is SD Express capable but this driver port does not currently > include that feature yet. > Based on downstream driver by raspberry foundation maintained kernel. > > Signed-off-by: Andrea della Porta <andrea.porta@suse.com> > --- > drivers/mmc/host/sdhci-brcmstb.c | 81 ++++++++++++++++++++++++++++++++ > 1 file changed, 81 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c > index 9053526fa212..13a1017d53c5 100644 > --- a/drivers/mmc/host/sdhci-brcmstb.c > +++ b/drivers/mmc/host/sdhci-brcmstb.c > @@ -30,6 +30,24 @@ > > #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 > > +#define SDIO_CFG_CQ_CAPABILITY 0x4c > +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) > + > +#define SDIO_CFG_CTRL 0x0 > +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) > +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) > + > +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac > +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) > +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) > + > +#define MMC_CAP_HSE_MASK (MMC_CAP2_HS200_1_8V_SDR | \ > + MMC_CAP2_HS200_1_2V_SDR | \ > + MMC_CAP2_HS400_1_8V | \ > + MMC_CAP2_HS400_1_2V) This could be simplified either with MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V or MMC_CAP2_HS200 | MMC_CAP2_HS400 > + > +#define MMC_CAP_UHS_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) There is already a MMC_CAP_UHS define, but according to the code this is not intended. It looks more like a mask of all UHS modes equal and above 50 MHz. The name or at least a comment should reflect this. > + > struct sdhci_brcmstb_priv { > void __iomem *cfg_regs; > unsigned int flags; > @@ -38,6 +56,7 @@ struct sdhci_brcmstb_priv { > }; > > struct brcmstb_match_priv { > + void (*cfginit)(struct sdhci_host *host); > void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); > struct sdhci_ops *ops; > const unsigned int flags; > @@ -139,6 +158,17 @@ static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) > sdhci_enable_clk(host, clk); > } > > +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode, > + unsigned short vdd) > +{ > + struct mmc_host *mmc = host->mmc; > + > + if (!IS_ERR(mmc->supply.vmmc)) > + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); > + > + sdhci_set_power_noreg(host, mode, vdd); > +} > + > static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, > unsigned int timing) > { > @@ -168,6 +198,40 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, > sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); > } > > +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) > +{ > + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); > + u32 hsemmc_mask = MMC_CAP_HSE_MASK; > + u32 uhs_mask = MMC_CAP_UHS_MASK; > + u32 reg, base_clk_mhz; > + > + /* > + * If we support a speed that requires tuning, > + * then select the delay line PHY as the clock source. > + */ > + if ((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask)) { > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); > + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; > + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); > + } > + > + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || > + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { > + /* Force presence */ > + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); > + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; > + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); > + } > + > + /* Guesstimate the timer frequency (controller base clock) */ > + base_clk_mhz = max_t(u32, clk_get_rate(pltfm_host->clk) / (1000 * 1000), 1); > + reg = SDIO_CFG_CQ_CAPABILITY_FMUL | base_clk_mhz; > + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CQ_CAPABILITY); > +} > + > static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) > { > sdhci_dumpregs(mmc_priv(mmc)); > @@ -200,6 +264,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { > .set_uhs_signaling = sdhci_set_uhs_signaling, > }; > > +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { > + .set_clock = sdhci_set_clock, > + .set_power = sdhci_brcmstb_set_power, > + .set_bus_width = sdhci_set_bus_width, > + .reset = sdhci_reset, > + .set_uhs_signaling = sdhci_set_uhs_signaling, > +}; > + > static struct sdhci_ops sdhci_brcmstb_ops_7216 = { > .set_clock = sdhci_brcmstb_set_clock, > .set_bus_width = sdhci_set_bus_width, > @@ -214,6 +286,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { > .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, > }; > > +static const struct brcmstb_match_priv match_priv_2712 = { > + .cfginit = sdhci_brcmstb_cfginit_2712, > + .ops = &sdhci_brcmstb_ops_2712, > +}; > + > static struct brcmstb_match_priv match_priv_7425 = { > .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | > BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, > @@ -238,6 +315,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = { > }; > > static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { > + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, > { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, > { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, > { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, > @@ -370,6 +448,9 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) > (host->mmc->caps2 & MMC_CAP2_HS400_ES)) > host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; > > + if (match_priv->cfginit) > + match_priv->cfginit(host); > + > /* > * Supply the existing CAPS, but clear the UHS modes. This > * will allow these modes to be specified by device tree
diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index 9053526fa212..13a1017d53c5 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -30,6 +30,24 @@ #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 +#define SDIO_CFG_CQ_CAPABILITY 0x4c +#define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) + +#define SDIO_CFG_CTRL 0x0 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) + +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31) +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0) + +#define MMC_CAP_HSE_MASK (MMC_CAP2_HS200_1_8V_SDR | \ + MMC_CAP2_HS200_1_2V_SDR | \ + MMC_CAP2_HS400_1_8V | \ + MMC_CAP2_HS400_1_2V) + +#define MMC_CAP_UHS_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; @@ -38,6 +56,7 @@ struct sdhci_brcmstb_priv { }; struct brcmstb_match_priv { + void (*cfginit)(struct sdhci_host *host); void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); struct sdhci_ops *ops; const unsigned int flags; @@ -139,6 +158,17 @@ static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_enable_clk(host, clk); } +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode, + unsigned short vdd) +{ + struct mmc_host *mmc = host->mmc; + + if (!IS_ERR(mmc->supply.vmmc)) + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); + + sdhci_set_power_noreg(host, mode, vdd); +} + static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { @@ -168,6 +198,40 @@ static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host); + u32 hsemmc_mask = MMC_CAP_HSE_MASK; + u32 uhs_mask = MMC_CAP_UHS_MASK; + u32 reg, base_clk_mhz; + + /* + * If we support a speed that requires tuning, + * then select the delay line PHY as the clock source. + */ + if ((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask)) { + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE; + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE); + } + + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) { + /* Force presence */ + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV; + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL); + } + + /* Guesstimate the timer frequency (controller base clock) */ + base_clk_mhz = max_t(u32, clk_get_rate(pltfm_host->clk) / (1000 * 1000), 1); + reg = SDIO_CFG_CQ_CAPABILITY_FMUL | base_clk_mhz; + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CQ_CAPABILITY); +} + static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -200,6 +264,14 @@ static struct sdhci_ops sdhci_brcmstb_ops = { .set_uhs_signaling = sdhci_set_uhs_signaling, }; +static struct sdhci_ops sdhci_brcmstb_ops_2712 = { + .set_clock = sdhci_set_clock, + .set_power = sdhci_brcmstb_set_power, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_clock = sdhci_brcmstb_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -214,6 +286,11 @@ static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; +static const struct brcmstb_match_priv match_priv_2712 = { + .cfginit = sdhci_brcmstb_cfginit_2712, + .ops = &sdhci_brcmstb_ops_2712, +}; + static struct brcmstb_match_priv match_priv_7425 = { .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -238,6 +315,7 @@ static struct brcmstb_match_priv match_priv_74165b0 = { }; static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 }, { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, @@ -370,6 +448,9 @@ static int sdhci_brcmstb_probe(struct platform_device *pdev) (host->mmc->caps2 & MMC_CAP2_HS400_ES)) host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; + if (match_priv->cfginit) + match_priv->cfginit(host); + /* * Supply the existing CAPS, but clear the UHS modes. This * will allow these modes to be specified by device tree
Broadcom BCM2712 SoC has an SDHCI card controller using the SDIO CFG register block present on other STB chips. Add support for BCM2712 SD capabilities of this chipset. The silicon is SD Express capable but this driver port does not currently include that feature yet. Based on downstream driver by raspberry foundation maintained kernel. Signed-off-by: Andrea della Porta <andrea.porta@suse.com> --- drivers/mmc/host/sdhci-brcmstb.c | 81 ++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)