| Message ID | 20230125104520.89684-1-quic_kathirav@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add minimal boot support for IPQ5332 | expand |
On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote: > From: Kathiravan T <quic_kathirav@quicinc.com> > > Add support for the global clock controller found on IPQ5332 SoC. > > Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> > --- > drivers/clk/qcom/Kconfig | 7 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gcc-ipq5332.c | 3954 ++++++++++++++++++++++++++++++++ > 3 files changed, 3962 insertions(+) > create mode 100644 drivers/clk/qcom/gcc-ipq5332.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 70d43f0a8919..1d300c89ecfc 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -141,6 +141,13 @@ config IPQ_GCC_4019 > Say Y if you want to use peripheral devices such as UART, SPI, > i2c, USB, SD/eMMC, etc. > > +config IPQ_GCC_5332 > + tristate "IPQ5332 Global Clock Controller" depends on ARM64 || COMPILE_TEST Best regards, Krzysztof
On 1/25/2023 4:44 PM, Krzysztof Kozlowski wrote: > On 25/01/2023 11:45, Kathiravan Thirumoorthy wrote: >> From: Kathiravan T <quic_kathirav@quicinc.com> >> >> Add support for the global clock controller found on IPQ5332 SoC. >> >> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> >> --- >> drivers/clk/qcom/Kconfig | 7 + >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/gcc-ipq5332.c | 3954 ++++++++++++++++++++++++++++++++ >> 3 files changed, 3962 insertions(+) >> create mode 100644 drivers/clk/qcom/gcc-ipq5332.c >> >> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig >> index 70d43f0a8919..1d300c89ecfc 100644 >> --- a/drivers/clk/qcom/Kconfig >> +++ b/drivers/clk/qcom/Kconfig >> @@ -141,6 +141,13 @@ config IPQ_GCC_4019 >> Say Y if you want to use peripheral devices such as UART, SPI, >> i2c, USB, SD/eMMC, etc. >> >> +config IPQ_GCC_5332 >> + tristate "IPQ5332 Global Clock Controller" > depends on ARM64 || COMPILE_TEST Ack. > > > > Best regards, > Krzysztof Thanks, Kathiravan T.
Quoting Kathiravan Thirumoorthy (2023-01-25 02:45:15) > diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c > new file mode 100644 > index 000000000000..8351096a4d32 > --- /dev/null > +++ b/drivers/clk/qcom/gcc-ipq5332.c > @@ -0,0 +1,3954 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/regmap.h> [...] > + > +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { > + F(24000000, P_XO, 1, 0, 0), > + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), > + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { > + .cmd_rcgr = 0x31004, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gcc_parent_map_0, > + .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, > + .clkr.hw.init = &(const struct clk_init_data){ > + .name = "gcc_pcnoc_bfdcd_clk_src", > + .parent_data = gcc_parent_data_0, > + .num_parents = ARRAY_SIZE(gcc_parent_data_0), > + .ops = &clk_rcg2_ops, > + .flags = CLK_IS_CRITICAL, Why not just turn these clks on in probe and never register them with the framework? That saves some memory for clks that there is no desire to control from linux. This is an RCG, so in theory the frequency can change, but does it really? Usually bus clks are controlled by the interconnect driver.
On 1/26/2023 2:24 AM, Stephen Boyd wrote: > Quoting Kathiravan Thirumoorthy (2023-01-25 02:45:15) >> diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c >> new file mode 100644 >> index 000000000000..8351096a4d32 >> --- /dev/null >> +++ b/drivers/clk/qcom/gcc-ipq5332.c >> @@ -0,0 +1,3954 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +#include <linux/clk-provider.h> >> +#include <linux/module.h> >> +#include <linux/of_device.h> >> +#include <linux/regmap.h> > [...] >> + >> +static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = { >> + F(24000000, P_XO, 1, 0, 0), >> + F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), >> + F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = { >> + .cmd_rcgr = 0x31004, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = gcc_parent_map_0, >> + .freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src, >> + .clkr.hw.init = &(const struct clk_init_data){ >> + .name = "gcc_pcnoc_bfdcd_clk_src", >> + .parent_data = gcc_parent_data_0, >> + .num_parents = ARRAY_SIZE(gcc_parent_data_0), >> + .ops = &clk_rcg2_ops, >> + .flags = CLK_IS_CRITICAL, > Why not just turn these clks on in probe and never register them with > the framework? That saves some memory for clks that there is no desire > to control from linux. This is an RCG, so in theory the frequency can > change, but does it really? Usually bus clks are controlled by the > interconnect driver. Thanks Stephen for reviewing the patch. I will look into this and make changes appropriately in V2.
From: Kathiravan T <quic_kathirav@quicinc.com> The IPQ5332 is Qualcomm's 802.11ax SoC for Routers, Gateways and Access Points. This series adds minimal board boot support for ipq5332-mi01.2 board. Also, this series depends on the below patch https://lore.kernel.org/linux-arm-msm/20230120082631.22053-1-quic_kathirav@quicinc.com/ Kathiravan T (10): dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl pinctrl: qcom: Introduce IPQ5332 TLMM driver clk: qcom: Add STROMER PLUS PLL type for IPQ5332 dt-bindings: clock: Add Qualcomm IPQ5332 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC dt-bindings: qcom: add ipq5332 boards dt-bindings: firmware: document IPQ5332 SCM dt-bindings: mmc: sdhci-msm: add IPQ5332 compatible arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support arm64: defconfig: Enable IPQ5332 SoC base configs .../devicetree/bindings/arm/qcom.yaml | 7 + .../bindings/clock/qcom,ipq5332-gcc.yaml | 55 + .../bindings/firmware/qcom,scm.yaml | 1 + .../devicetree/bindings/mmc/sdhci-msm.yaml | 1 + .../pinctrl/qcom,ipq5332-pinctrl.yaml | 134 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 71 + arch/arm64/boot/dts/qcom/ipq5332.dtsi | 273 ++ arch/arm64/configs/defconfig | 2 + drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 11 + drivers/clk/qcom/clk-alpha-pll.h | 1 + drivers/clk/qcom/gcc-ipq5332.c | 3954 +++++++++++++++++ drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-ipq5332.c | 1008 +++++ include/dt-bindings/clock/qcom,gcc-ipq5332.h | 359 ++ 18 files changed, 5897 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-pinctrl.yaml create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi create mode 100644 drivers/clk/qcom/gcc-ipq5332.c create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5332.c create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5332.h