| Message ID | 1562859668-14209-7-git-send-email-gokulsri@codeaurora.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | remoteproc: qcom: q6v5-wcss: Add support for secure pil | expand |
Quoting Gokul Sriram Palanisamy (2019-07-11 08:41:02) > Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. > > Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> > --- Acked-by: Stephen Boyd <sboyd@kernel.org>
On Thu, Jul 11, 2019 at 09:11:02PM +0530, Gokul Sriram Palanisamy wrote: > Add binding for WCSSAON reset required for Q6v5 reset on IPQ8074 SoC. > > Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org> > Signed-off-by: Sricharan R <sricharan@codeaurora.org> > Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org> > --- > include/dt-bindings/clock/qcom,gcc-ipq8074.h | 1 + > 1 file changed, 1 insertion(+) Acked-by: Rob Herring <robh@kernel.org>
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h b/include/dt-bindings/clock/qcom,gcc-ipq8074.h index 4de4811..04e1f57 100644 --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h @@ -362,5 +362,6 @@ #define GCC_PCIE1_AXI_SLAVE_ARES 128 #define GCC_PCIE1_AHB_ARES 129 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES 130 +#define GCC_WCSSAON_RESET 131 #endif