| Message ID | 20221118122539.384993-4-brgl@bgdev.pl (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | serial: qcom-geni-serial: implement support for SE DMA | expand |
On 18/11/2022 13:25, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Keep the #define symbols aligned for better readability. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > drivers/tty/serial/qcom_geni_serial.c | 62 +++++++++++++-------------- > 1 file changed, 31 insertions(+), 31 deletions(-) > > diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c > index 7af5df6833c7..97ee7c074b79 100644 > --- a/drivers/tty/serial/qcom_geni_serial.c > +++ b/drivers/tty/serial/qcom_geni_serial.c > @@ -39,57 +39,57 @@ > #define SE_UART_MANUAL_RFR 0x2ac > > /* SE_UART_TRANS_CFG */ > -#define UART_TX_PAR_EN BIT(0) > -#define UART_CTS_MASK BIT(1) > +#define UART_TX_PAR_EN BIT(0) > +#define UART_CTS_MASK BIT(1) > > /* SE_UART_TX_STOP_BIT_LEN */ > -#define TX_STOP_BIT_LEN_1 0 > -#define TX_STOP_BIT_LEN_2 2 > +#define TX_STOP_BIT_LEN_1 0 > +#define TX_STOP_BIT_LEN_2 2 > > /* SE_UART_RX_TRANS_CFG */ > -#define UART_RX_PAR_EN BIT(3) > +#define UART_RX_PAR_EN BIT(3) > > /* SE_UART_RX_WORD_LEN */ > -#define RX_WORD_LEN_MASK GENMASK(9, 0) > +#define RX_WORD_LEN_MASK GENMASK(9, 0) > > /* SE_UART_RX_STALE_CNT */ > -#define RX_STALE_CNT GENMASK(23, 0) > +#define RX_STALE_CNT GENMASK(23, 0) > > /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ > -#define PAR_CALC_EN BIT(0) > -#define PAR_EVEN 0x00 > -#define PAR_ODD 0x01 > -#define PAR_SPACE 0x10 > +#define PAR_CALC_EN BIT(0) > +#define PAR_EVEN 0x00 > +#define PAR_ODD 0x01 > +#define PAR_SPACE 0x10 > > /* SE_UART_MANUAL_RFR register fields */ > -#define UART_MANUAL_RFR_EN BIT(31) > -#define UART_RFR_NOT_READY BIT(1) > -#define UART_RFR_READY BIT(0) > +#define UART_MANUAL_RFR_EN BIT(31) > +#define UART_RFR_NOT_READY BIT(1) > +#define UART_RFR_READY BIT(0) > > /* UART M_CMD OP codes */ > -#define UART_START_TX 0x1 > +#define UART_START_TX 0x1 > /* UART S_CMD OP codes */ > -#define UART_START_READ 0x1 > - > -#define UART_OVERSAMPLING 32 > -#define STALE_TIMEOUT 16 > -#define DEFAULT_BITS_PER_CHAR 10 > -#define GENI_UART_CONS_PORTS 1 > -#define GENI_UART_PORTS 3 > -#define DEF_FIFO_DEPTH_WORDS 16 > -#define DEF_TX_WM 2 > -#define DEF_FIFO_WIDTH_BITS 32 > -#define UART_RX_WM 2 > +#define UART_START_READ 0x1 > + > +#define UART_OVERSAMPLING 32 > +#define STALE_TIMEOUT 16 > +#define DEFAULT_BITS_PER_CHAR 10 > +#define GENI_UART_CONS_PORTS 1 > +#define GENI_UART_PORTS 3 > +#define DEF_FIFO_DEPTH_WORDS 16 > +#define DEF_TX_WM 2 > +#define DEF_FIFO_WIDTH_BITS 32 > +#define UART_RX_WM 2 > > /* SE_UART_LOOPBACK_CFG */ > -#define RX_TX_SORTED BIT(0) > -#define CTS_RTS_SORTED BIT(1) > -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) > +#define RX_TX_SORTED BIT(0) > +#define CTS_RTS_SORTED BIT(1) > +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) > > /* UART pin swap value */ > -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) > +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) > #define IO_MACRO_IO0_SEL 0x3 > -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) > +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) > #define IO_MACRO_IO2_IO3_SWAP 0x4640 > > /* We always configure 4 bytes per FIFO word */
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c index 7af5df6833c7..97ee7c074b79 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -39,57 +39,57 @@ #define SE_UART_MANUAL_RFR 0x2ac /* SE_UART_TRANS_CFG */ -#define UART_TX_PAR_EN BIT(0) -#define UART_CTS_MASK BIT(1) +#define UART_TX_PAR_EN BIT(0) +#define UART_CTS_MASK BIT(1) /* SE_UART_TX_STOP_BIT_LEN */ -#define TX_STOP_BIT_LEN_1 0 -#define TX_STOP_BIT_LEN_2 2 +#define TX_STOP_BIT_LEN_1 0 +#define TX_STOP_BIT_LEN_2 2 /* SE_UART_RX_TRANS_CFG */ -#define UART_RX_PAR_EN BIT(3) +#define UART_RX_PAR_EN BIT(3) /* SE_UART_RX_WORD_LEN */ -#define RX_WORD_LEN_MASK GENMASK(9, 0) +#define RX_WORD_LEN_MASK GENMASK(9, 0) /* SE_UART_RX_STALE_CNT */ -#define RX_STALE_CNT GENMASK(23, 0) +#define RX_STALE_CNT GENMASK(23, 0) /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ -#define PAR_CALC_EN BIT(0) -#define PAR_EVEN 0x00 -#define PAR_ODD 0x01 -#define PAR_SPACE 0x10 +#define PAR_CALC_EN BIT(0) +#define PAR_EVEN 0x00 +#define PAR_ODD 0x01 +#define PAR_SPACE 0x10 /* SE_UART_MANUAL_RFR register fields */ -#define UART_MANUAL_RFR_EN BIT(31) -#define UART_RFR_NOT_READY BIT(1) -#define UART_RFR_READY BIT(0) +#define UART_MANUAL_RFR_EN BIT(31) +#define UART_RFR_NOT_READY BIT(1) +#define UART_RFR_READY BIT(0) /* UART M_CMD OP codes */ -#define UART_START_TX 0x1 +#define UART_START_TX 0x1 /* UART S_CMD OP codes */ -#define UART_START_READ 0x1 - -#define UART_OVERSAMPLING 32 -#define STALE_TIMEOUT 16 -#define DEFAULT_BITS_PER_CHAR 10 -#define GENI_UART_CONS_PORTS 1 -#define GENI_UART_PORTS 3 -#define DEF_FIFO_DEPTH_WORDS 16 -#define DEF_TX_WM 2 -#define DEF_FIFO_WIDTH_BITS 32 -#define UART_RX_WM 2 +#define UART_START_READ 0x1 + +#define UART_OVERSAMPLING 32 +#define STALE_TIMEOUT 16 +#define DEFAULT_BITS_PER_CHAR 10 +#define GENI_UART_CONS_PORTS 1 +#define GENI_UART_PORTS 3 +#define DEF_FIFO_DEPTH_WORDS 16 +#define DEF_TX_WM 2 +#define DEF_FIFO_WIDTH_BITS 32 +#define UART_RX_WM 2 /* SE_UART_LOOPBACK_CFG */ -#define RX_TX_SORTED BIT(0) -#define CTS_RTS_SORTED BIT(1) -#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) +#define RX_TX_SORTED BIT(0) +#define CTS_RTS_SORTED BIT(1) +#define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) /* UART pin swap value */ -#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) +#define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) #define IO_MACRO_IO0_SEL 0x3 -#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) +#define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) #define IO_MACRO_IO2_IO3_SWAP 0x4640 /* We always configure 4 bytes per FIFO word */