| Message ID | 20221202155738.383301-3-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v3,1/3] arm64: dts: qcom: sdm845-db845c: fix audio codec interrupt pin name | expand |
Hi, On Fri, Dec 2, 2022 at 7:57 AM Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> wrote: > > Each board should define pin drive/bias for used busses. All boards > using SPI0 (db845c and cheza) already do it, so drop the bias/drive > strength from SoC DTSI. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > --- > > Cc: Doug Anderson <dianders@chromium.org> > > Changes since v2: > 1. New patch. > --- > arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- > 1 file changed, 2 deletions(-) Reviewed-by: Douglas Anderson <dianders@chromium.org> It's hard to review device trees without noticing things that are inefficient / wrong. In case you want any others for your list: a) As written today, `sdm845-db845c.dts` doesn't actually need to override the `pinctrl` of `spi0` since it's the default. So you could remove two extra lines of device tree. b) Officially, db845c actually _should_ be overriding the pinctrl and we should be doing something like what we did for sc7180 where we have different definitions for "cs" and "cs_gpio" for the SPI lines. That's because db845c is actually using "cs-gpio" mode for this SPI part and thus GPIO3 should be marked as being "gpio", not "qup0". It doesn't really matter functionality-wise on Linux because the Qualcomm pinctrl driver will automatically re-mux the pin as a GPIO the moment the SPI core tries to use it as such, but it's a little ugly.
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index e6019009533e..1a7999843dd6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2785,8 +2785,6 @@ qup_i2c15_default: qup-i2c15-default-state { qup_spi0_default: qup-spi0-default-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "qup0"; - drive-strength = <6>; - bias-disable; }; qup_spi1_default: qup-spi1-default-state {
Each board should define pin drive/bias for used busses. All boards using SPI0 (db845c and cheza) already do it, so drop the bias/drive strength from SoC DTSI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Cc: Doug Anderson <dianders@chromium.org> Changes since v2: 1. New patch. --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 -- 1 file changed, 2 deletions(-)