| Message ID | 20230613001004.3426676-3-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm/dpu: another catalog rework | expand |
On 6/12/2023 5:09 PM, Dmitry Baryshkov wrote: > Each MERGE_3D block has just two registers. Correct the block length > accordingly. > > Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- LGTM, Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
On 2023-06-13 03:09:41, Dmitry Baryshkov wrote: > Each MERGE_3D block has just two registers. Correct the block length > accordingly. > > Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Indeed, and that patch wasn't even introducing the register writes - this only happened in commit 9ffd0e8569937 ("drm/msm/dpu: setup merge modes in merge_3d block"). Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 36ba3f58dcdf..0de507d4d7b7 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -508,7 +508,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { > #define MERGE_3D_BLK(_name, _id, _base) \ > {\ > .name = _name, .id = _id, \ > - .base = _base, .len = 0x100, \ > + .base = _base, .len = 0x8, \ > .features = MERGE_3D_SM8150_MASK, \ > .sblk = NULL \ > } > -- > 2.39.2 >
On 16/06/2023 01:22, Marijn Suijten wrote: > On 2023-06-13 03:09:41, Dmitry Baryshkov wrote: >> Each MERGE_3D block has just two registers. Correct the block length >> accordingly. >> >> Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block") >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > Indeed, and that patch wasn't even introducing the register writes - > this only happened in commit 9ffd0e8569937 ("drm/msm/dpu: setup merge > modes in merge_3d block"). Yep. Vendor dts declares merge 3d block length to be 0x100, which I blindly copied. > > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> > >> --- >> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 36ba3f58dcdf..0de507d4d7b7 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -508,7 +508,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { >> #define MERGE_3D_BLK(_name, _id, _base) \ >> {\ >> .name = _name, .id = _id, \ >> - .base = _base, .len = 0x100, \ >> + .base = _base, .len = 0x8, \ >> .features = MERGE_3D_SM8150_MASK, \ >> .sblk = NULL \ >> } >> -- >> 2.39.2 >>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 36ba3f58dcdf..0de507d4d7b7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -508,7 +508,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { #define MERGE_3D_BLK(_name, _id, _base) \ {\ .name = _name, .id = _id, \ - .base = _base, .len = 0x100, \ + .base = _base, .len = 0x8, \ .features = MERGE_3D_SM8150_MASK, \ .sblk = NULL \ }
Each MERGE_3D block has just two registers. Correct the block length accordingly. Fixes: 4369c93cf36b ("drm/msm/dpu: initial support for merge3D hardware block") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)