| Message ID | 20231213162856.188566-4-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | a25d2dbb68aab84a4431d382d6a21539ed6760e5 |
| Headers | show |
| Series | arm64: dts: qcom: few improvements | expand |
Le 13/12/2023 à 17:28, Krzysztof Kozlowski a écrit : > Pin configuration for Soundwire bus should be set in Soundwire > controller nodes, not in the associated macro codec node. This > placement change should not have big impact in general, because macro > codec is a clock provider for Soundwire controller, thus its devices is > probed first. However it will have impact for disabled Soundwire buses, > e.g. WSA2, because after this change the pins will be left in default > state. > > We also follow similar approach in newer SoCs, like Qualcomm SM8650. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++-------- > 1 file changed, 12 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index 1f06fd33d1ce..d8f79b5895f5 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -2050,8 +2050,6 @@ lpass_wsa2macro: codec@6aa0000 { > > #clock-cells = <0>; > clock-output-names = "wsa2-mclk"; > - pinctrl-names = "default"; > - pinctrl-0 = <&wsa2_swr_active>; > #sound-dai-cells = <1>; > }; > > @@ -2063,6 +2061,9 @@ swr3: soundwire-controller@6ab0000 { > clock-names = "iface"; > label = "WSA2"; > > + pinctrl-0 = <&wsa2_swr_active>; > + pinctrl-names = "default"; > + > qcom,din-ports = <4>; > qcom,dout-ports = <9>; > > @@ -2096,8 +2097,6 @@ lpass_rxmacro: codec@6ac0000 { > > #clock-cells = <0>; > clock-output-names = "mclk"; > - pinctrl-names = "default"; > - pinctrl-0 = <&rx_swr_active>; > #sound-dai-cells = <1>; > }; > > @@ -2109,6 +2108,9 @@ swr1: soundwire-controller@6ad0000 { > clock-names = "iface"; > label = "RX"; > > + pinctrl-0 = <&rx_swr_active>; > + pinctrl-names = "default"; > + > qcom,din-ports = <1>; > qcom,dout-ports = <11>; > > @@ -2142,8 +2144,6 @@ lpass_txmacro: codec@6ae0000 { > > #clock-cells = <0>; > clock-output-names = "mclk"; > - pinctrl-names = "default"; > - pinctrl-0 = <&tx_swr_active>; > #sound-dai-cells = <1>; > }; > > @@ -2161,8 +2161,6 @@ lpass_wsamacro: codec@6b00000 { > > #clock-cells = <0>; > clock-output-names = "mclk"; > - pinctrl-names = "default"; > - pinctrl-0 = <&wsa_swr_active>; > #sound-dai-cells = <1>; > }; > > @@ -2174,6 +2172,9 @@ swr0: soundwire-controller@6b10000 { > clock-names = "iface"; > label = "WSA"; > > + pinctrl-0 = <&wsa_swr_active>; > + pinctrl-names = "default"; > + > qcom,din-ports = <4>; > qcom,dout-ports = <9>; > > @@ -2203,6 +2204,9 @@ swr2: soundwire-controller@6d30000 { > clock-names = "iface"; > label = "TX"; > > + pinctrl-0 = <&tx_swr_active>; > + pinctrl-names = "default"; > + > qcom,din-ports = <4>; > qcom,dout-ports = <0>; > qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1f06fd33d1ce..d8f79b5895f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2050,8 +2050,6 @@ lpass_wsa2macro: codec@6aa0000 { #clock-cells = <0>; clock-output-names = "wsa2-mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa2_swr_active>; #sound-dai-cells = <1>; }; @@ -2063,6 +2061,9 @@ swr3: soundwire-controller@6ab0000 { clock-names = "iface"; label = "WSA2"; + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -2096,8 +2097,6 @@ lpass_rxmacro: codec@6ac0000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&rx_swr_active>; #sound-dai-cells = <1>; }; @@ -2109,6 +2108,9 @@ swr1: soundwire-controller@6ad0000 { clock-names = "iface"; label = "RX"; + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <1>; qcom,dout-ports = <11>; @@ -2142,8 +2144,6 @@ lpass_txmacro: codec@6ae0000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&tx_swr_active>; #sound-dai-cells = <1>; }; @@ -2161,8 +2161,6 @@ lpass_wsamacro: codec@6b00000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa_swr_active>; #sound-dai-cells = <1>; }; @@ -2174,6 +2172,9 @@ swr0: soundwire-controller@6b10000 { clock-names = "iface"; label = "WSA"; + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -2203,6 +2204,9 @@ swr2: soundwire-controller@6d30000 { clock-names = "iface"; label = "TX"; + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <0>; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
Pin configuration for Soundwire bus should be set in Soundwire controller nodes, not in the associated macro codec node. This placement change should not have big impact in general, because macro codec is a clock provider for Soundwire controller, thus its devices is probed first. However it will have impact for disabled Soundwire buses, e.g. WSA2, because after this change the pins will be left in default state. We also follow similar approach in newer SoCs, like Qualcomm SM8650. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-)