| Message ID | 20240124-pcie-aux-clk-fix-v1-4-d8a4852b6ba6@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Drop PCIE_AUX_CLK from the PCIe PHY nodes of Qcom SoCs | expand |
On 24/01/2024 08:36, Manivannan Sadhasivam wrote: > On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the > PCIe link enters L1SS state. On those platforms, a dedicated > PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block > doesn't require any other "aux" clock, including PCIE_AUX_CLK which only > required by the PCIe controller. > > Historically, the DTs of the platforms requiring "aux" clock passed > PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms > that do not require this dedicated "aux" clock mistakenly started passing > the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed > both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks. > > So to clean up this mess, let's remove the newly introduced "phy_aux" clock > and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that > require it. For the platforms that do not require a dedicated "aux" clock, > the clock is removed from DT. > > While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for > SC7280 SoC which was earlier using the compatible > "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and > also restructure the "clock-names" property for the affected platforms. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 24-01-24, 13:06, Manivannan Sadhasivam wrote: > On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the > PCIe link enters L1SS state. On those platforms, a dedicated > PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block > doesn't require any other "aux" clock, including PCIE_AUX_CLK which only > required by the PCIe controller. > > Historically, the DTs of the platforms requiring "aux" clock passed > PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms > that do not require this dedicated "aux" clock mistakenly started passing > the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed > both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks. > > So to clean up this mess, let's remove the newly introduced "phy_aux" clock > and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that > require it. For the platforms that do not require a dedicated "aux" clock, > the clock is removed from DT. > > While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for > SC7280 SoC which was earlier using the compatible > "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and > also restructure the "clock-names" property for the affected platforms. This one fails to apply for me
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 6c03f2d5fca3..2396a457f9c8 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy + - qcom,sc7280-qmp-pcie-phy - qcom,sc8180x-qmp-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy @@ -44,19 +45,12 @@ properties: maxItems: 2 clocks: - minItems: 5 - maxItems: 7 + minItems: 4 + maxItems: 6 clock-names: - minItems: 5 - items: - - const: aux - - const: cfg_ahb - - const: ref - - enum: [rchng, refgen] - - const: pipe - - const: pipediv2 - - const: phy_aux + minItems: 4 + maxItems: 6 power-domains: maxItems: 1 @@ -130,6 +124,28 @@ allOf: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-qmp-pcie-phy + - qcom,sm8350-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x1-pcie-phy + - qcom,sm8450-qmp-gen3x2-pcie-phy + - qcom,sm8550-qmp-gen3x2-pcie-phy + - qcom,sm8650-qmp-gen3x2-pcie-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_ahb + - const: ref + - enum: [rchng, refgen] + - const: pipe + - if: properties: compatible: @@ -144,19 +160,19 @@ allOf: - qcom,sm8250-qmp-gen3x1-pcie-phy - qcom,sm8250-qmp-gen3x2-pcie-phy - qcom,sm8250-qmp-modem-pcie-phy - - qcom,sm8350-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen3x1-pcie-phy - - qcom,sm8450-qmp-gen3x2-pcie-phy - - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - - qcom,sm8650-qmp-gen3x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy then: properties: clocks: maxItems: 5 clock-names: - maxItems: 5 + items: + - const: aux + - const: cfg_ahb + - const: ref + - enum: [rchng, refgen] + - const: pipe - if: properties: @@ -169,9 +185,14 @@ allOf: then: properties: clocks: - minItems: 6 + maxItems: 5 clock-names: - minItems: 6 + items: + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: pipediv2 - if: properties: @@ -183,9 +204,15 @@ allOf: then: properties: clocks: - minItems: 7 + minItems: 6 clock-names: - minItems: 7 + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: pipediv2 - if: properties: @@ -215,13 +242,12 @@ examples: compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; reg = <0x01c18000 0x2000>; - clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, - <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2B_PIPE_CLK>, <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; power-domains = <&gcc PCIE_2B_GDSC>; @@ -242,13 +268,12 @@ examples: compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; reg = <0x01c24000 0x2000>, <0x01c26000 0x2000>; - clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, - <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, + clocks = <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, <&gcc GCC_PCIE_2A_PIPE_CLK>, <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; - clock-names = "aux", "cfg_ahb", "ref", "rchng", + clock-names = "cfg_ahb", "ref", "rchng", "pipe", "pipediv2"; power-domains = <&gcc PCIE_2A_GDSC>;
On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the PCIe link enters L1SS state. On those platforms, a dedicated PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block doesn't require any other "aux" clock, including PCIE_AUX_CLK which only required by the PCIe controller. Historically, the DTs of the platforms requiring "aux" clock passed PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms that do not require this dedicated "aux" clock mistakenly started passing the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks. So to clean up this mess, let's remove the newly introduced "phy_aux" clock and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that require it. For the platforms that do not require a dedicated "aux" clock, the clock is removed from DT. While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for SC7280 SoC which was earlier using the compatible "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and also restructure the "clock-names" property for the affected platforms. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 79 ++++++++++++++-------- 1 file changed, 52 insertions(+), 27 deletions(-)