| Message ID | 20240408-dispcc-dp-clocks-v1-1-f9e44902c28d@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: dispcc: fix DisplayPort link clocks | expand |
Quoting Dmitry Baryshkov (2024-04-08 04:47:04) > On SM8450 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. The subject says "fix", but does this fix anything, or simply optimize? Is something broken by having the frequency table?
On 08/04/2024 13:47, Dmitry Baryshkov wrote: > On SM8450 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. > > Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- > 1 file changed, 4 insertions(+), 16 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c > index 92e9c4e7b13d..49bb4f58c391 100644 > --- a/drivers/clk/qcom/dispcc-sm8450.c > +++ b/drivers/clk/qcom/dispcc-sm8450.c > @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { > - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { > .cmd_rcgr = 0x819c, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx0_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx1_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx2_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_3, > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > .clkr.hw.init = &(struct clk_init_data) { > .name = "disp_cc_mdss_dptx3_link_clk_src", > .parent_data = disp_cc_parent_data_3, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> I can't test, but I assume you tested on your HDK8450 Thanks, Neil
On Wed, 10 Apr 2024 at 19:27, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > On 08/04/2024 13:47, Dmitry Baryshkov wrote: > > On SM8450 DisplayPort link clocks use frequency tables inherited from > > the vendor kernel, it is not applicable in the upstream kernel. Drop > > frequency tables and use clk_byte2_ops for those clocks. > > > > Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- > > 1 file changed, 4 insertions(+), 16 deletions(-) > > > > diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c > > index 92e9c4e7b13d..49bb4f58c391 100644 > > --- a/drivers/clk/qcom/dispcc-sm8450.c > > +++ b/drivers/clk/qcom/dispcc-sm8450.c > > @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { > > }, > > }; > > > > -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { > > - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > > - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > > - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > > - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), > > - { } > > -}; > > - > > static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { > > .cmd_rcgr = 0x819c, > > .mnd_width = 0, > > .hid_width = 5, > > .parent_map = disp_cc_parent_map_3, > > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > > .clkr.hw.init = &(struct clk_init_data) { > > .name = "disp_cc_mdss_dptx0_link_clk_src", > > .parent_data = disp_cc_parent_data_3, > > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > > .flags = CLK_SET_RATE_PARENT, > > - .ops = &clk_rcg2_ops, > > + .ops = &clk_byte2_ops, > > }, > > }; > > > > @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { > > .mnd_width = 0, > > .hid_width = 5, > > .parent_map = disp_cc_parent_map_3, > > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > > .clkr.hw.init = &(struct clk_init_data) { > > .name = "disp_cc_mdss_dptx1_link_clk_src", > > .parent_data = disp_cc_parent_data_3, > > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > > .flags = CLK_SET_RATE_PARENT, > > - .ops = &clk_rcg2_ops, > > + .ops = &clk_byte2_ops, > > }, > > }; > > > > @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { > > .mnd_width = 0, > > .hid_width = 5, > > .parent_map = disp_cc_parent_map_3, > > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > > .clkr.hw.init = &(struct clk_init_data) { > > .name = "disp_cc_mdss_dptx2_link_clk_src", > > .parent_data = disp_cc_parent_data_3, > > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > > .flags = CLK_SET_RATE_PARENT, > > - .ops = &clk_rcg2_ops, > > + .ops = &clk_byte2_ops, > > }, > > }; > > > > @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { > > .mnd_width = 0, > > .hid_width = 5, > > .parent_map = disp_cc_parent_map_3, > > - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, > > .clkr.hw.init = &(struct clk_init_data) { > > .name = "disp_cc_mdss_dptx3_link_clk_src", > > .parent_data = disp_cc_parent_data_3, > > .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), > > .flags = CLK_SET_RATE_PARENT, > > - .ops = &clk_rcg2_ops, > > + .ops = &clk_byte2_ops, > > }, > > }; > > > > > > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> > > I can't test, but I assume you tested on your HDK8450 That's how I stumbled upon it. I was not able to test other patches in the series, but granted the similarity I assume that they should work in the same way.
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c index 92e9c4e7b13d..49bb4f58c391 100644 --- a/drivers/clk/qcom/dispcc-sm8450.c +++ b/drivers/clk/qcom/dispcc-sm8450.c @@ -309,26 +309,17 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dptx0_link_clk_src[] = { - F(162000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP0_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dptx0_link_clk_src = { .cmd_rcgr = 0x819c, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx0_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -382,13 +373,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx1_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -442,13 +432,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx2_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, }; @@ -502,13 +491,12 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_link_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_3, - .freq_tbl = ftbl_disp_cc_mdss_dptx0_link_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "disp_cc_mdss_dptx3_link_clk_src", .parent_data = disp_cc_parent_data_3, .num_parents = ARRAY_SIZE(disp_cc_parent_data_3), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, };
On SM8450 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 16fb89f92ec4 ("clk: qcom: Add support for Display Clock Controller on SM8450") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm8450.c | 20 ++++---------------- 1 file changed, 4 insertions(+), 16 deletions(-)