| Message ID | 20240408-dispcc-dp-clocks-v1-2-f9e44902c28d@linaro.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | clk: qcom: dispcc: fix DisplayPort link clocks | expand |
On 08/04/2024 13:47, Dmitry Baryshkov wrote: > On SM6350 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. > > Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- > 1 file changed, 1 insertion(+), 10 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c > index 839435362010..e4b7464c4d0e 100644 > --- a/drivers/clk/qcom/dispcc-sm6350.c > +++ b/drivers/clk/qcom/dispcc-sm6350.c > @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { > - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > .cmd_rcgr = 0x10f8, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > - .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, > .clkr.hw.init = &(struct clk_init_data){ > .name = "disp_cc_mdss_dp_link_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; > > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
On Mon Apr 8, 2024 at 1:47 PM CEST, Dmitry Baryshkov wrote: > On SM6350 DisplayPort link clocks use frequency tables inherited from > the vendor kernel, it is not applicable in the upstream kernel. Drop > frequency tables and use clk_byte2_ops for those clocks. > > Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Appears to fix this non-critical error when enabling DisplayPort. msm-dp-display ae90000.displayport-controller: _opp_config_clk_single: failed to set clock rate: -22 And DisplayPort (over USB-C) continues to work as expected, thanks! Tested-by: Luca Weiss <luca.weiss@fairphone.com> For completeness, I wrote something about this also on #linux-msm IRC on March 22nd. > Hi, I'm trying to get displayport to work on sm6350 but hitting a > weird issue regarding link clk frequency. For the requested link > rate=540000 in dp_ctrl_enable_mainlink_clocks we call > dev_pm_opp_set_rate with target_freq=540000000 (clk name: > disp_cc_mdss_dp_link_clk) but the clk_round_rate there makes this into > freq=810000 and subsequently qmp_dp_link_clk_determine_rate fails > because that's not a valid frequency, only for example 810000000. > Without any debug statements the visible error in kernel log is: > "msm-dp-display ae90000.displayport-controller: > _opp_config_clk_single: failed to set clock rate: -22" > > So somewhere there seems to be confusion between how many zeroes > should be where.. But not sure how this is working on other SoCs, I > don't see anything much different for my SoC > > Kernel base is 6.8.1 fwiw > > clk_round_rate behavior feels correct as > ftbl_disp_cc_mdss_dp_link_clk_src lists the frequencies as > 162000/270000/540000/810000 so it rounds it to the highest available > frequency of the clock Regards Luca > --- > drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- > 1 file changed, 1 insertion(+), 10 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c > index 839435362010..e4b7464c4d0e 100644 > --- a/drivers/clk/qcom/dispcc-sm6350.c > +++ b/drivers/clk/qcom/dispcc-sm6350.c > @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { > }, > }; > > -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { > - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > - { } > -}; > - > static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > .cmd_rcgr = 0x10f8, > .mnd_width = 0, > .hid_width = 5, > .parent_map = disp_cc_parent_map_0, > - .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, > .clkr.hw.init = &(struct clk_init_data){ > .name = "disp_cc_mdss_dp_link_clk_src", > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, > - .ops = &clk_rcg2_ops, > + .ops = &clk_byte2_ops, > }, > }; >
diff --git a/drivers/clk/qcom/dispcc-sm6350.c b/drivers/clk/qcom/dispcc-sm6350.c index 839435362010..e4b7464c4d0e 100644 --- a/drivers/clk/qcom/dispcc-sm6350.c +++ b/drivers/clk/qcom/dispcc-sm6350.c @@ -221,26 +221,17 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { }, }; -static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { - F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), - { } -}; - static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { .cmd_rcgr = 0x10f8, .mnd_width = 0, .hid_width = 5, .parent_map = disp_cc_parent_map_0, - .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "disp_cc_mdss_dp_link_clk_src", .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE, - .ops = &clk_rcg2_ops, + .ops = &clk_byte2_ops, }, };
On SM6350 DisplayPort link clocks use frequency tables inherited from the vendor kernel, it is not applicable in the upstream kernel. Drop frequency tables and use clk_byte2_ops for those clocks. Fixes: 837519775f1d ("clk: qcom: Add display clock controller driver for SM6350") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> --- drivers/clk/qcom/dispcc-sm6350.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)