| Message ID | 20240416105650.2626-1-quic_vdadhani@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1] arm64: dts: qcom: sc7280: Remove CTS/RTS configuration | expand |
On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote: > Remove CTS and RTS pinctrl configuration for UART5 node as > it's designed for debug UART for all the board variants of the > sc7280 chipset. > > Also change compatible string to debug UART. This change has little to do with the SoC design though and is dependent on the usage on a given board, right? Also the QCM6490 datasheet mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR. But at least consistency-wise this change makes sense, in practically all other SoCs one UART is marked as geni-debug-uart. But with this patch you should then also remove some overrides that are placed in various boards already? arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible = "qcom,geni-debug-uart"; arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible = "qcom,geni-debug-uart"; arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible = "qcom,geni-debug-uart"; arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible = "qcom,geni-debug-uart"; arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible = "qcom,geni-debug-uart"; Regards Luca > > Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") > Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 38c183b2bb26..2a6b4c4639d1 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1440,12 +1440,12 @@ > }; > > uart5: serial@994000 { > - compatible = "qcom,geni-uart"; > + compatible = "qcom,geni-debug-uart"; > reg = <0 0x00994000 0 0x4000>; > clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > clock-names = "se"; > pinctrl-names = "default"; > - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; > + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; > interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&rpmhpd SC7280_CX>; > operating-points-v2 = <&qup_opp_table>; > @@ -5397,16 +5397,6 @@ > function = "qup04"; > }; > > - qup_uart5_cts: qup-uart5-cts-state { > - pins = "gpio20"; > - function = "qup05"; > - }; > - > - qup_uart5_rts: qup-uart5-rts-state { > - pins = "gpio21"; > - function = "qup05"; > - }; > - > qup_uart5_tx: qup-uart5-tx-state { > pins = "gpio22"; > function = "qup05";
On 4/16/24 13:38, Luca Weiss wrote: > On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote: >> Remove CTS and RTS pinctrl configuration for UART5 node as >> it's designed for debug UART for all the board variants of the >> sc7280 chipset. >> >> Also change compatible string to debug UART. > > This change has little to do with the SoC design though and is dependent > on the usage on a given board, right? Also the QCM6490 datasheet > mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR. Yeah, using it as a debug uart doesn't rule out flow control I don't think > > But at least consistency-wise this change makes sense, in practically > all other SoCs one UART is marked as geni-debug-uart. > > But with this patch you should then also remove some overrides that are > placed in various boards already? > > arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible = "qcom,geni-debug-uart"; Definitely Konrad
On Tue, Apr 16, 2024 at 04:26:50PM +0530, Viken Dadhaniya wrote: > Remove CTS and RTS pinctrl configuration for UART5 node as > it's designed for debug UART for all the board variants of the > sc7280 chipset. > > Also change compatible string to debug UART. > Why are you posting this on the public mailing list without first addressing the feedback and questions I gave you on the internal review list? Now you wasted the time of our community members, just to receive the same feedback I gave you last week. Regards, Bjorn > Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") > Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ > 1 file changed, 2 insertions(+), 12 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 38c183b2bb26..2a6b4c4639d1 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1440,12 +1440,12 @@ > }; > > uart5: serial@994000 { > - compatible = "qcom,geni-uart"; > + compatible = "qcom,geni-debug-uart"; > reg = <0 0x00994000 0 0x4000>; > clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; > clock-names = "se"; > pinctrl-names = "default"; > - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; > + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; > interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; > power-domains = <&rpmhpd SC7280_CX>; > operating-points-v2 = <&qup_opp_table>; > @@ -5397,16 +5397,6 @@ > function = "qup04"; > }; > > - qup_uart5_cts: qup-uart5-cts-state { > - pins = "gpio20"; > - function = "qup05"; > - }; > - > - qup_uart5_rts: qup-uart5-rts-state { > - pins = "gpio21"; > - function = "qup05"; > - }; > - > qup_uart5_tx: qup-uart5-tx-state { > pins = "gpio22"; > function = "qup05"; > -- > 2.17.1 >
On 4/16/2024 5:08 PM, Luca Weiss wrote: > On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote: >> Remove CTS and RTS pinctrl configuration for UART5 node as >> it's designed for debug UART for all the board variants of the >> sc7280 chipset. >> >> Also change compatible string to debug UART. > > This change has little to do with the SoC design though and is dependent > on the usage on a given board, right? Also the QCM6490 datasheet > mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR. > > But at least consistency-wise this change makes sense, in practically > all other SoCs one UART is marked as geni-debug-uart. > > But with this patch you should then also remove some overrides that are > placed in various boards already? > > arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible = "qcom,geni-debug-uart"; > arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible = "qcom,geni-debug-uart"; > > Regards > Luca > Updated in V2. >> >> Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") >> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ >> 1 file changed, 2 insertions(+), 12 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 38c183b2bb26..2a6b4c4639d1 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1440,12 +1440,12 @@ >> }; >> >> uart5: serial@994000 { >> - compatible = "qcom,geni-uart"; >> + compatible = "qcom,geni-debug-uart"; >> reg = <0 0x00994000 0 0x4000>; >> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> clock-names = "se"; >> pinctrl-names = "default"; >> - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; >> + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; >> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >> power-domains = <&rpmhpd SC7280_CX>; >> operating-points-v2 = <&qup_opp_table>; >> @@ -5397,16 +5397,6 @@ >> function = "qup04"; >> }; >> >> - qup_uart5_cts: qup-uart5-cts-state { >> - pins = "gpio20"; >> - function = "qup05"; >> - }; >> - >> - qup_uart5_rts: qup-uart5-rts-state { >> - pins = "gpio21"; >> - function = "qup05"; >> - }; >> - >> qup_uart5_tx: qup-uart5-tx-state { >> pins = "gpio22"; >> function = "qup05"; >
On 4/16/2024 8:09 PM, Konrad Dybcio wrote: > > > On 4/16/24 13:38, Luca Weiss wrote: >> On Tue Apr 16, 2024 at 12:56 PM CEST, Viken Dadhaniya wrote: >>> Remove CTS and RTS pinctrl configuration for UART5 node as >>> it's designed for debug UART for all the board variants of the >>> sc7280 chipset. >>> >>> Also change compatible string to debug UART. >> >> This change has little to do with the SoC design though and is dependent >> on the usage on a given board, right? Also the QCM6490 datasheet >> mentions gpio21 & gpio22 can be used for UART_CTS and UART_RFR. > > Yeah, using it as a debug uart doesn't rule out flow control I don't think > >> >> But at least consistency-wise this change makes sense, in practically >> all other SoCs one UART is marked as geni-debug-uart. >> >> But with this patch you should then also remove some overrides that are >> placed in various boards already? >> >> arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts: compatible = >> "qcom,geni-debug-uart"; >> arch/arm64/boot/dts/qcom/qcm6490-idp.dts: compatible = >> "qcom,geni-debug-uart"; >> arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts: compatible = >> "qcom,geni-debug-uart"; >> arch/arm64/boot/dts/qcom/sc7280-idp.dtsi: compatible = >> "qcom,geni-debug-uart"; >> arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi: compatible = >> "qcom,geni-debug-uart"; > > Definitely Updated in V2. > > Konrad
On 4/17/2024 10:09 AM, Bjorn Andersson wrote: > On Tue, Apr 16, 2024 at 04:26:50PM +0530, Viken Dadhaniya wrote: >> Remove CTS and RTS pinctrl configuration for UART5 node as >> it's designed for debug UART for all the board variants of the >> sc7280 chipset. >> >> Also change compatible string to debug UART. >> > > Why are you posting this on the public mailing list without first > addressing the feedback and questions I gave you on the internal review > list? > > Now you wasted the time of our community members, just to receive the > same feedback I gave you last week. > > Regards, > Bjorn > Sorry, I missed you feedback due to incorrect mail filler. >> Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") >> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ >> 1 file changed, 2 insertions(+), 12 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 38c183b2bb26..2a6b4c4639d1 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1440,12 +1440,12 @@ >> }; >> >> uart5: serial@994000 { >> - compatible = "qcom,geni-uart"; >> + compatible = "qcom,geni-debug-uart"; >> reg = <0 0x00994000 0 0x4000>; >> clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; >> clock-names = "se"; >> pinctrl-names = "default"; >> - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; >> + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; >> interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; >> power-domains = <&rpmhpd SC7280_CX>; >> operating-points-v2 = <&qup_opp_table>; >> @@ -5397,16 +5397,6 @@ >> function = "qup04"; >> }; >> >> - qup_uart5_cts: qup-uart5-cts-state { >> - pins = "gpio20"; >> - function = "qup05"; >> - }; >> - >> - qup_uart5_rts: qup-uart5-rts-state { >> - pins = "gpio21"; >> - function = "qup05"; >> - }; >> - >> qup_uart5_tx: qup-uart5-tx-state { >> pins = "gpio22"; >> function = "qup05"; >> -- >> 2.17.1 >>
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 38c183b2bb26..2a6b4c4639d1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1440,12 +1440,12 @@ }; uart5: serial@994000 { - compatible = "qcom,geni-uart"; + compatible = "qcom,geni-debug-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; + pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SC7280_CX>; operating-points-v2 = <&qup_opp_table>; @@ -5397,16 +5397,6 @@ function = "qup04"; }; - qup_uart5_cts: qup-uart5-cts-state { - pins = "gpio20"; - function = "qup05"; - }; - - qup_uart5_rts: qup-uart5-rts-state { - pins = "gpio21"; - function = "qup05"; - }; - qup_uart5_tx: qup-uart5-tx-state { pins = "gpio22"; function = "qup05";
Remove CTS and RTS pinctrl configuration for UART5 node as it's designed for debug UART for all the board variants of the sc7280 chipset. Also change compatible string to debug UART. Fixes: 38cd93f413fd ("arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node") Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)