| Message ID | 20240225-gcc-ipq5018-register-fixes-v1-3-3c191404d9f0@gmail.com (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: qcom: gcc-ipq5018: fix some register offsets | expand |
On Sun, 25 Feb 2024 at 19:34, Gabor Juhos <j4g8y7@gmail.com> wrote: > > The current register offset used for the GCC_UBI0_AXI_ARES reset > seems wrong. Or at least, the downstream driver uses [1] the same > offset which is used for other the GCC_UBI0_*_ARES resets. > > Change the code to use the same offset used in the downstream > driver and also specify the reset bit explicitly to use the > same format as the followup entries. > > 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 > > Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") > Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> > --- > drivers/clk/qcom/gcc-ipq5018.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
On 2/25/2024 11:02 PM, Gabor Juhos wrote: > The current register offset used for the GCC_UBI0_AXI_ARES reset > seems wrong. Or at least, the downstream driver uses [1] the same > offset which is used for other the GCC_UBI0_*_ARES resets. > > Change the code to use the same offset used in the downstream > driver and also specify the reset bit explicitly to use the > same format as the followup entries. > > 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> > > Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") > Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> > --- > drivers/clk/qcom/gcc-ipq5018.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c > index 5e81cfa77293a..e2bd54826a4ce 100644 > --- a/drivers/clk/qcom/gcc-ipq5018.c > +++ b/drivers/clk/qcom/gcc-ipq5018.c > @@ -3632,7 +3632,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { > [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, > [GCC_TCSR_BCR] = { 0x28000, 0 }, > [GCC_TLMM_BCR] = { 0x34000, 0 }, > - [GCC_UBI0_AXI_ARES] = { 0x680}, > + [GCC_UBI0_AXI_ARES] = { 0x68010, 0 }, > [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, > [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, > [GCC_UBI0_DBG_ARES] = { 0x68010, 3 }, >
diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 5e81cfa77293a..e2bd54826a4ce 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3632,7 +3632,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets[] = { [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, [GCC_TCSR_BCR] = { 0x28000, 0 }, [GCC_TLMM_BCR] = { 0x34000, 0 }, - [GCC_UBI0_AXI_ARES] = { 0x680}, + [GCC_UBI0_AXI_ARES] = { 0x68010, 0 }, [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, [GCC_UBI0_DBG_ARES] = { 0x68010, 3 },
The current register offset used for the GCC_UBI0_AXI_ARES reset seems wrong. Or at least, the downstream driver uses [1] the same offset which is used for other the GCC_UBI0_*_ARES resets. Change the code to use the same offset used in the downstream driver and also specify the reset bit explicitly to use the same format as the followup entries. 1. https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r4/drivers/clk/qcom/gcc-ipq5018.c?ref_type=heads#L3773 Fixes: e3fdbef1bab8 ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018") Signed-off-by: Gabor Juhos <j4g8y7@gmail.com> --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)