| Message ID | 20240314-imx95-blk-ctl-v4-1-d23de23b6ff2@nxp.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add support i.MX95 BLK CTL module clock features | expand |
On Thu, Mar 14, 2024 at 09:25:10PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > The i.MX95 VPU_CSR contains control and status registers for VPU > status, pending transaction status, and clock gating controls. > > This patch is to add clock features for VPU CSR. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 ++++++++++++++++++++++ > include/dt-bindings/clock/nxp,imx95-clock.h | 14 ++++++ > 2 files changed, 64 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > new file mode 100644 > index 000000000000..4a1c6dcfe3f8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nxp,imx95-vpu-csr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX95 VPUMIX Block Control > + > +maintainers: > + - Peng Fan <peng.fan@nxp.com> > + > +properties: > + compatible: > + items: > + - const: nxp,imx95-vpu-csr > + - const: syscon > + > + reg: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + description: > + The clock consumer should specify the desired clock by having the clock > + ID in its "clocks" phandle cell. See > + include/dt-bindings/clock/nxp,imx95-clock.h > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + syscon@4c410000 { > + compatible = "nxp,imx95-vpu-csr", "syscon"; > + reg = <0x4c410000 0x10000>; > + #clock-cells = <1>; > + clocks = <&scmi_clk 114>; > + power-domains = <&scmi_devpd 21>; > + }; > +... > diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h > new file mode 100644 > index 000000000000..9d8f0a6d12d0 > --- /dev/null > +++ b/include/dt-bindings/clock/nxp,imx95-clock.h > @@ -0,0 +1,14 @@ > +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ > +/* > + * Copyright 2024 NXP > + */ > + > +#ifndef __DT_BINDINGS_CLOCK_IMX95_H > +#define __DT_BINDINGS_CLOCK_IMX95_H > + > +#define IMX95_CLK_VPUBLK_WAVE 0 > +#define IMX95_CLK_VPUBLK_JPEG_ENC 1 > +#define IMX95_CLK_VPUBLK_JPEG_DEC 2 > +#define IMX95_CLK_VPUBLK_END 3 If this number can change, then it is not ABI and doesn't go in this header. With that dropped, Reviewed-by: Rob Herring <robh@kernel.org>
On 14/03/2024 14:25, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > The i.MX95 VPU_CSR contains control and status registers for VPU > status, pending transaction status, and clock gating controls. > > This patch is to add clock features for VPU CSR. Fix the subject prefix. You mess with people's filters. > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 ++++++++++++++++++++++ > include/dt-bindings/clock/nxp,imx95-clock.h | 14 ++++++ > 2 files changed, 64 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > new file mode 100644 > index 000000000000..4a1c6dcfe3f8 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/nxp,imx95-vpu-csr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX95 VPUMIX Block Control > + > +maintainers: > + - Peng Fan <peng.fan@nxp.com> > + > +properties: > + compatible: > + items: > + - const: nxp,imx95-vpu-csr > + - const: syscon > + > + reg: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + '#clock-cells': > + const: 1 > + description: > + The clock consumer should specify the desired clock by having the clock > + ID in its "clocks" phandle cell. See > + include/dt-bindings/clock/nxp,imx95-clock.h > + > +required: > + - compatible > + - reg > + - '#clock-cells' > + > +additionalProperties: false > + > +examples: > + - | > + syscon@4c410000 { > + compatible = "nxp,imx95-vpu-csr", "syscon"; > + reg = <0x4c410000 0x10000>; > + #clock-cells = <1>; > + clocks = <&scmi_clk 114>; > + power-domains = <&scmi_devpd 21>; > + }; > +... > diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h > new file mode 100644 > index 000000000000..9d8f0a6d12d0 > --- /dev/null > +++ b/include/dt-bindings/clock/nxp,imx95-clock.h If the header is only for clock IDs for this binding, then keep the same filename as binding filename. Best regards, Krzysztof
> Subject: Re: [PATCH v4 1/6] dt-bindindgs: clock: nxp: support i.MX95 VPU > CSR module > > On 14/03/2024 14:25, Peng Fan (OSS) wrote: > > From: Peng Fan <peng.fan@nxp.com> > > > > The i.MX95 VPU_CSR contains control and status registers for VPU > > status, pending transaction status, and clock gating controls. > > > > This patch is to add clock features for VPU CSR. > > Fix the subject prefix. You mess with people's filters. Sorry, a typo error. Will fix it. > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > --- > > .../bindings/clock/nxp,imx95-vpu-csr.yaml | 50 > ++++++++++++++++++++++ > > include/dt-bindings/clock/nxp,imx95-clock.h | 14 ++++++ > > 2 files changed, 64 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > new file mode 100644 > > index 000000000000..4a1c6dcfe3f8 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml > > @@ -0,0 +1,50 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fschemas%2Fclock%2Fnxp%2Cimx95-vpu- > csr.yaml%23&data=05%7C > > > +02%7Cpeng.fan%40nxp.com%7Cbd64d1b5d1784bdb6df508dc453133ca%7 > C686ea1d3 > > > +bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638461324818682648%7CUnk > nown%7CTWF > > > +pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX > VCI6 > > > +Mn0%3D%7C0%7C%7C%7C&sdata=PtStE2Y%2BnS4HpesF9wE66t8bh0Qmg > 3s3y4aERwhSr > > +Mo%3D&reserved=0 > > +$schema: > > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi > > +cetree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=05%7C02%7Cpeng.fan%40nx > > > +p.com%7Cbd64d1b5d1784bdb6df508dc453133ca%7C686ea1d3bc2b4c6fa > 92cd99c5c > > > +301635%7C0%7C0%7C638461324818692719%7CUnknown%7CTWFpbGZs > b3d8eyJWIjoiM > > > +C4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7 > C%7C%7 > > > +C&sdata=zWKRFnTPTwLZvtOvOrFUo%2FNlqPKRqRIEYCrztlfhzAU%3D&reserv > ed=0 > > + > > +title: NXP i.MX95 VPUMIX Block Control > > + > > +maintainers: > > + - Peng Fan <peng.fan@nxp.com> > > + > > +properties: > > + compatible: > > + items: > > + - const: nxp,imx95-vpu-csr > > + - const: syscon > > + > > + reg: > > + maxItems: 1 > > + > > + power-domains: > > + maxItems: 1 > > + > > + clocks: > > + maxItems: 1 > > + > > + '#clock-cells': > > + const: 1 > > + description: > > + The clock consumer should specify the desired clock by having the > clock > > + ID in its "clocks" phandle cell. See > > + include/dt-bindings/clock/nxp,imx95-clock.h > > + > > +required: > > + - compatible > > + - reg > > + - '#clock-cells' > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + syscon@4c410000 { > > + compatible = "nxp,imx95-vpu-csr", "syscon"; > > + reg = <0x4c410000 0x10000>; > > + #clock-cells = <1>; > > + clocks = <&scmi_clk 114>; > > + power-domains = <&scmi_devpd 21>; > > + }; > > +... > > diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h > > b/include/dt-bindings/clock/nxp,imx95-clock.h > > new file mode 100644 > > index 000000000000..9d8f0a6d12d0 > > --- /dev/null > > +++ b/include/dt-bindings/clock/nxp,imx95-clock.h > > If the header is only for clock IDs for this binding, then keep the same > filename as binding filename. No, this file will also include other IDs in following patches. Thanks, Peng. > > Best regards, > Krzysztof
diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml new file mode 100644 index 000000000000..4a1c6dcfe3f8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nxp,imx95-vpu-csr.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/nxp,imx95-vpu-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX95 VPUMIX Block Control + +maintainers: + - Peng Fan <peng.fan@nxp.com> + +properties: + compatible: + items: + - const: nxp,imx95-vpu-csr + - const: syscon + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See + include/dt-bindings/clock/nxp,imx95-clock.h + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + syscon@4c410000 { + compatible = "nxp,imx95-vpu-csr", "syscon"; + reg = <0x4c410000 0x10000>; + #clock-cells = <1>; + clocks = <&scmi_clk 114>; + power-domains = <&scmi_devpd 21>; + }; +... diff --git a/include/dt-bindings/clock/nxp,imx95-clock.h b/include/dt-bindings/clock/nxp,imx95-clock.h new file mode 100644 index 000000000000..9d8f0a6d12d0 --- /dev/null +++ b/include/dt-bindings/clock/nxp,imx95-clock.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2024 NXP + */ + +#ifndef __DT_BINDINGS_CLOCK_IMX95_H +#define __DT_BINDINGS_CLOCK_IMX95_H + +#define IMX95_CLK_VPUBLK_WAVE 0 +#define IMX95_CLK_VPUBLK_JPEG_ENC 1 +#define IMX95_CLK_VPUBLK_JPEG_DEC 2 +#define IMX95_CLK_VPUBLK_END 3 + +#endif /* __DT_BINDINGS_CLOCK_IMX95_H */