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Patch Series A/R/T S/W/F Date Submitter Delegate State
fpga: dfl-afu-region: Add overflow checks for region size and offset fpga: dfl-afu-region: Add overflow checks for region size and offset - 1 - --- 2023-02-06 k1rh4.lee@gmail.com New
[v11,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 3 - --- 2023-01-15 matthew.gerlach@linux.intel.com New
[v11,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2023-01-15 matthew.gerlach@linux.intel.com New
[v11,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-15 matthew.gerlach@linux.intel.com New
[v11,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-15 matthew.gerlach@linux.intel.com New
[v10,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-10 matthew.gerlach@linux.intel.com New
[v10,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2023-01-10 matthew.gerlach@linux.intel.com New
[v10,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-10 matthew.gerlach@linux.intel.com New
[v10,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-10 matthew.gerlach@linux.intel.com New
[v9,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-04 matthew.gerlach@linux.intel.com New
[v9,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2023-01-04 matthew.gerlach@linux.intel.com New
[v9,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-04 matthew.gerlach@linux.intel.com New
[v9,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2023-01-04 matthew.gerlach@linux.intel.com New
[v8,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2022-12-28 matthew.gerlach@linux.intel.com New
[v8,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-28 matthew.gerlach@linux.intel.com New
[v8,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2022-12-28 matthew.gerlach@linux.intel.com New
[v8,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-28 matthew.gerlach@linux.intel.com New
[v7,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-20 matthew.gerlach@linux.intel.com New
[v7,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-20 matthew.gerlach@linux.intel.com New
[v7,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 2 - --- 2022-12-20 matthew.gerlach@linux.intel.com New
[v7,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-20 matthew.gerlach@linux.intel.com New
[v6,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v6,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v6,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v6,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v5,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v5,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v5,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v5,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for UART driver - 1 - --- 2022-12-09 matthew.gerlach@linux.intel.com New
[v4,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-20 matthew.gerlach@linux.intel.com New
[v4,3/4] fpga: dfl: add basic support DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-20 matthew.gerlach@linux.intel.com New
[v4,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-20 matthew.gerlach@linux.intel.com New
[v4,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-20 matthew.gerlach@linux.intel.com New
[v3,4/4] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-04 matthew.gerlach@linux.intel.com New
[v3,3/4] fpga: dfl: add basic support for DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-04 matthew.gerlach@linux.intel.com New
[v3,2/4] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-04 matthew.gerlach@linux.intel.com New
[v3,1/4] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-10-04 matthew.gerlach@linux.intel.com New
[v2,6/6] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-23 matthew.gerlach@linux.intel.com New
[v2,5/6] fpga: dfl: parse the location of the feature's registers from DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-23 matthew.gerlach@linux.intel.com New
[v2,4/6] fpga: dfl: add generic support for MSIX interrupts Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-23 matthew.gerlach@linux.intel.com New
[v2,3/6] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-23 matthew.gerlach@linux.intel.com New
[v2,2/6] fpga: dfl: Move the DFH definitions Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-23 matthew.gerlach@linux.intel.com New
[v2,1/6] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-23 matthew.gerlach@linux.intel.com New
[v1,5/5] tty: serial: 8250: add DFL bus driver for Altera 16550. Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-06 matthew.gerlach@linux.intel.com New
[v1,4/5] fpga: dfl: add generic support for MSIX interrupts Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-06 matthew.gerlach@linux.intel.com New
[v1,3/5] fpga: dfl: Add DFHv1 Register Definitions Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-06 matthew.gerlach@linux.intel.com New
[v1,2/5] fpga: dfl: Move the DFH definitions Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-06 matthew.gerlach@linux.intel.com New
[v1,1/5] Documentation: fpga: dfl: Add documentation for DFHv1 Enhance definition of DFH and use enhancements for uart driver - - - --- 2022-09-06 matthew.gerlach@linux.intel.com New
[v4] fpga: dfl-pci: Add IDs for Intel N6000, N6001 and C6100 cards [v4] fpga: dfl-pci: Add IDs for Intel N6000, N6001 and C6100 cards 2 1 1 --- 2022-07-19 matthew.gerlach@linux.intel.com New
[v3,2/2] fpga: dfl-pci: Add IDs for Intel N6000, N6001 and C6100 cards Add PCIE device IDs for Intel DFL cards 1 1 1 --- 2022-07-07 matthew.gerlach@linux.intel.com New
[v3,1/2] Documentation: fpga: dfl: add PCI Identification documentation Add PCIE device IDs for Intel DFL cards - 1 - --- 2022-07-07 matthew.gerlach@linux.intel.com New
[3/3] add debugfs interface for fpga config complete timeout fpga: fpga-mgr: Add support for DebugFS for FPGA Manager Framework - - - --- 2022-05-17 adrian.ho.yin.ng@intel.com New
[2/3] fpga: doc: documentation for FPGA debugfs fpga: fpga-mgr: Add support for DebugFS for FPGA Manager Framework - - - --- 2022-05-17 adrian.ho.yin.ng@intel.com New
[1/3] fpga: Implement DebugFS for FPGA Manager Framework fpga: fpga-mgr: Add support for DebugFS for FPGA Manager Framework - - - --- 2022-05-17 adrian.ho.yin.ng@intel.com New
[v2,2/2] drivers: fpga: dfl-pci: Add PCIE device IDs for Intel DFL cards Add PCIE device IDs for Intel DFL cards - - - --- 2022-03-03 matthew.gerlach@linux.intel.com New
[v2,1/2] Documentation: fpga: dfl: add PCI Identification documentation Add PCIE device IDs for Intel DFL cards - - - --- 2022-03-03 matthew.gerlach@linux.intel.com New
fpga: dfl: pci: gracefully handle misconfigured port entries fpga: dfl: pci: gracefully handle misconfigured port entries - - - --- 2021-04-20 matthew.gerlach@linux.intel.com New
[v3,2/2] spi: altera: Add DFL bus driver for Altera API Controller spi: altera: Add DFL bus support for Altera SPI - - - --- 2021-04-16 matthew.gerlach@linux.intel.com New
[v3,1/2] spi: altera: separate core code from platform code spi: altera: Add DFL bus support for Altera SPI - - - --- 2021-04-16 matthew.gerlach@linux.intel.com New
[v2,2/2] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card spi: add BMC support for Intel D5005 card 1 1 - --- 2021-04-13 matthew.gerlach@linux.intel.com New
[v2,1/2] spi: Add DFL bus driver for Altera SPI Master spi: add BMC support for Intel D5005 card - - - --- 2021-04-13 matthew.gerlach@linux.intel.com New
[3/3] hwmon: intel-m10-bmc-hwmon: add sensor support of Intel D5005 card fpga: dfl: add support for Intel D5005 card 1 - - --- 2021-04-05 matthew.gerlach@linux.intel.com New
[2/3] fpga: dfl: Add DFL bus driver for Altera SPI Master fpga: dfl: add support for Intel D5005 card - - - --- 2021-04-05 matthew.gerlach@linux.intel.com New
[1/3] fpga: dfl: pci: add DID for D5005 PAC cards fpga: dfl: add support for Intel D5005 card - - - --- 2021-04-05 matthew.gerlach@linux.intel.com New
[v4,2/2] fpga: dfl-pci: locate DFLs by PCIe vendor specific capability fpga: dfl: optional VSEC for start of dfl - - - --- 2020-12-03 matthew.gerlach@linux.intel.com Superseded
[v4,1/2] fpga: dfl: refactor cci_enumerate_feature_devs() fpga: dfl: optional VSEC for start of dfl 1 - - --- 2020-12-03 matthew.gerlach@linux.intel.com Superseded
[v3,2/2] fpga: dfl: look for vendor specific capability fpga: dfl: optional VSEC for start of dfl - - - --- 2020-11-24 matthew.gerlach@linux.intel.com Superseded
[v3,1/2] fpga: dfl: refactor cci_enumerate_feature_devs() fpga: dfl: optional VSEC for start of dfl - - - --- 2020-11-24 matthew.gerlach@linux.intel.com Superseded
[v2,2/2] fpga: dfl: look for vendor specific capability fpga: dfl: optional VSEC for start of dfl - - - --- 2020-11-18 matthew.gerlach@linux.intel.com Superseded
[v2,1/2] fpga: dfl: refactor cci_enumerate_feature_devs() fpga: dfl: optional VSEC for start of dfl - - - --- 2020-11-18 matthew.gerlach@linux.intel.com Superseded
[2/2] fpga: dfl: look for vendor specific capability fpga: dfl: optional VSEC for start of dfl - - - --- 2020-11-17 matthew.gerlach@linux.intel.com Superseded
[1/2] fpga: dfl: refactor cci_enumerate_feature_devs() fpga: dfl: optional VSEC for start of dfl - 1 - --- 2020-11-17 matthew.gerlach@linux.intel.com Superseded
[2/2] fpga: altera-cvp: Fix function definition argument fpga: altera-cvp: clean checkpatch faults - - - --- 2018-11-08 capetry.dev@gmail.com m0reeze Mainlined
[1/2] fpga: altera-cvp: Insert SPDX-License-Identifier fpga: altera-cvp: clean checkpatch faults - - - --- 2018-11-08 capetry.dev@gmail.com m0reeze Superseded
[v3,2/2] mtd: spi-nor: Altera ASMI Parallel II IP Core - - - --- 2017-10-19 matthew.gerlach@linux.intel.com Not Applicable
[v3,1/2] dt-bindings: mtd: Altera ASMI Parallel II IP Core 1 - - --- 2017-10-19 matthew.gerlach@linux.intel.com Not Applicable
[v2,3/3] mtd: spi-nor: add flag for reading dummy cycles from nv cfg reg - - - --- 2017-09-20 matthew.gerlach@linux.intel.com Superseded
[v2,2/3] mtd: spi-nor: Altera ASMI Parallel II IP Core - - - --- 2017-09-20 matthew.gerlach@linux.intel.com Superseded
[v2,1/3] dt-bindings: mtd: Altera ASMI Parallel II IP Core 1 - - --- 2017-09-20 matthew.gerlach@linux.intel.com Superseded
[3/3] fpga: intel: Add QSPI FPGA Management Entity Feature - - - --- 2017-08-06 matthew.gerlach@linux.intel.com Superseded
[2/2] mtd: spi-nor: Altera ASMI Parallel II IP Core - - - --- 2017-08-06 matthew.gerlach@linux.intel.com Superseded
[1/2] dt-bindings: mtd: Altera ASMI Parallel II IP Core - - - --- 2017-08-06 matthew.gerlach@linux.intel.com Superseded
[v2] fpga fr br: update supported version numbers - 1 - --- 2017-04-07 matthew.gerlach@linux.intel.com Accepted
fpga fr br: fix warning for unexpected version number - - - --- 2017-04-05 matthew.gerlach@linux.intel.com Superseded
[v6,4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP. 1 - - --- 2017-03-21 matthew.gerlach@linux.intel.com Accepted
[v6,3/4] fpga dt: bindings for Altera Partial Reconfiguration IP. 2 - - --- 2017-03-21 matthew.gerlach@linux.intel.com Accepted
[v6,2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. 1 - - --- 2017-03-21 matthew.gerlach@linux.intel.com Accepted
[v6,1/4] fpga: add config complete timeout - - - --- 2017-03-21 matthew.gerlach@linux.intel.com Accepted
[v5,4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP. - 1 - --- 2017-03-10 matthew.gerlach@linux.intel.com Superseded
[v5,3/4] fpga dt: bindings for Altera Partial Reconfiguration IP. 2 - - --- 2017-03-10 matthew.gerlach@linux.intel.com Superseded
[v5,2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. - 1 - --- 2017-03-10 matthew.gerlach@linux.intel.com Superseded
[v5,1/4] fpga: add config complete timeout 1 - - --- 2017-03-10 matthew.gerlach@linux.intel.com Superseded
[v4,4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP. - - - --- 2017-03-02 matthew.gerlach@linux.intel.com Superseded
[v4,3/4] fpga dt: bindings for Altera Partial Reconfiguration IP. 1 - - --- 2017-03-02 matthew.gerlach@linux.intel.com Superseded
[v4,2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. - - - --- 2017-03-02 matthew.gerlach@linux.intel.com Superseded
[v4,1/4] fpga: add config complete timeout - - - --- 2017-03-02 matthew.gerlach@linux.intel.com Superseded
fpga fr br: separate freeze bridge driver code - - - --- 2017-02-27 matthew.gerlach@linux.intel.com Accepted
[v2,4/4] fpga pr ip: Platform driver for Altera Partial Reconfiguration IP. - - - --- 2017-02-26 matthew.gerlach@linux.intel.com Superseded
[v2,3/4] fpga dt: bindings for Altera Partial Reconfiguration IP. - - - --- 2017-02-26 matthew.gerlach@linux.intel.com Superseded
[v2,2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP. - - - --- 2017-02-26 matthew.gerlach@linux.intel.com Superseded
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