[v2,071/106] ccs-pll: Add support for lane speed model

Message ID	20201007084557.25843-62-sakari.ailus@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=q2TO=DO=vger.kernel.org=linux-media-owner@kernel.org> From: Sakari Ailus <sakari.ailus@linux.intel.com> To: linux-media@vger.kernel.org Subject: [PATCH v2 071/106] ccs-pll: Add support for lane speed model Date: Wed, 7 Oct 2020 11:45:22 +0300 Message-Id: <20201007084557.25843-62-sakari.ailus@linux.intel.com> In-Reply-To: <20201007084557.25843-1-sakari.ailus@linux.intel.com> References: <20201007084505.25761-1-sakari.ailus@linux.intel.com> <20201007084557.25843-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	CCS driver \| expand [v2,000/106] CCS driver [v2,001/106] smiapp: Generate CCS register definitions and limits [v2,002/106] smiapp: Use CCS register flags [v2,003/106] smiapp: Calculate CCS limit offsets and limit buffer size [v2,004/106] smiapp: Remove macros for defining registers, merge definitions [v2,005/106] smiapp: Add macros for accessing CCS registers [v2,006/106] smiapp: Use MIPI CCS version and manufacturer ID information [v2,007/106] smiapp: Read CCS limit values [v2,008/106] smiapp: Switch to CCS limits [v2,009/106] smiapp: Obtain frame descriptor from CCS limits [v2,010/106] smiapp: Use CCS limits in reading data format descriptors [v2,011/106] smiapp: Use CCS limits in reading binning capabilities [v2,012/106] smiapp: Use CCS registers [v2,013/106] smiapp: Remove quirk function for writing a single 8-bit register [v2,014/106] smiapp: Rename register access functions [v2,015/106] smiapp: Internal rename to CCS [v2,016/106] smiapp: Differentiate CCS sensors from SMIA in subdev naming [v2,017/106] smiapp: Rename as "ccs" [v2,018/106] ccs: Remove profile concept [v2,019/106] ccs: Give all subdevs a function [v2,027/106] ccs: Request for "reset" GPIO [v2,028/106] ccs: Add MIPI CCS compatible strings [v2,029/106] ccs: Remove the I²C ID table [v2,030/106] ccs: Remove remaining support for platform data [v2,031/106] ccs: Make hwcfg part of the device specific struct [v2,032/106] ccs: Fix obtaining bus information from firmware [v2,033/106] ccs: Add CCS static data parser library [v2,034/106] ccs: Combine revision number major and minor into one [v2,035/106] ccs: Read CCS static data from firmware binaries [v2,036/106] ccs: Stop reading arrays after the first zero [v2,037/106] ccs: The functions to get compose or crop rectangle never return NULL [v2,038/106] ccs: Replace somewhat harsh internal checks based on BUG with WARN_ON [v2,039/106] ccs: Refactor register reading a little [v2,040/106] ccs: Make real to integer number conversion optional [v2,041/106] ccs: Move limit value real to integer conversion from read to access time [v2,042/106] ccs: Read ireal numbers correctly [v2,043/106] smiapp-pll: Rename as ccs-pll [v2,020/106] dt-bindings: nokia,smia: Fix link-frequencies documentation [v2,044/106] ccs-pll: Fix MODULE_LICENSE [v2,021/106] dt-bindings: nokia,smia: Make vana-supply optional [v2,045/106] ccs: Change my e-mail address [v2,022/106] dt-bindings: nokia,smia: Remove nokia,nvm-size property [v2,046/106] ccs: Add support for manufacturer regs from sensor and module files [v2,023/106] dt-bindings: nokia,smia: Convert to YAML [v2,047/106] ccs: Use static data read-only registers [v2,024/106] dt-bindings: nokia,smia: Use better active polarity for reset [v2,048/106] ccs: Clean up runtime PM usage [v2,025/106] dt-bindings: nokia,smia: Amend SMIA bindings with MIPI CCS support [v2,049/106] ccs: Wrap long lines, unwrap short ones [v2,026/106] dt-bindings: mipi-ccs: Add bus-type for C-PHY support [v2,050/106] ccs: Add device compatible identifiers for telling SMIA and CCS apart [v2,051/106] ccs: Use longer pre-I²C sleep for CCS compliant devices [v2,053/106] dt-bindings: mipi,ccs: Don't mention vana voltage [v2,052/106] ccs: Remove unnecessary delays from power-up sequence [v2,054/106] dt-bindings: mipi,ccs: Add vcore and vio supplies [v2,055/106] ccs: Use all regulators [v2,056/106] ccs-pll: Don't use div_u64 to divide a 32-bit number [v2,057/106] ccs-pll: Split limits and PLL configuration into front and back parts [v2,058/106] ccs-pll: Use correct VT divisor for calculating VT SYS divisor [v2,059/106] ccs-pll: End search if there are no better values available [v2,060/106] ccs-pll: Remove parallel bus support [v2,061/106] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY [v2,062/106] ccs-pll: Move the flags field down, away from 8-bit fields [v2,063/106] ccs-pll: Document the structs in the header as well as the function [v2,064/106] ccs-pll: Use the BIT macro [v2,065/106] ccs-pll: Begin calculation from OP system clock frequency [v2,066/106] ccs-pll: Fix condition for pre-PLL divider lower bound [v2,067/106] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search [v2,068/106] ccs-pll: Fix comment on check against maximum PLL multiplier [v2,069/106] ccs-pll: Fix check for PLL multiplier upper bound [v2,070/106] ccs-pll: Use explicit 32-bit unsigned type [v2,071/106] ccs-pll: Add support for lane speed model [v2,072/106] ccs: Add support for lane speed model [v2,073/106] ccs-pll: Add support for decoupled OP domain calculation [v2,074/106] ccs-pll: Add support for extended input PLL clock divider [v2,075/106] ccs-pll: Support two cycles per pixel on OP domain [v2,076/106] ccs-pll: Add support flexible OP PLL pixel clock divider [v2,077/106] ccs-pll: Add sanity checks [v2,078/106] ccs-pll: Add C-PHY support [v2,079/106] ccs-pll: Split off VT subtree calculation [v2,080/106] ccs-pll: Check for derating and overrating, support non-derating sensors [v2,081/106] ccs-pll: Better separate OP and VT sub-tree calculation [v2,082/106] ccs-pll: Print relevant information on PLL tree [v2,083/106] ccs-pll: Rework bounds checks [v2,084/106] ccs-pll: Make VT divisors 16-bit [v2,085/106] ccs-pll: Fix VT post-PLL divisor calculation [v2,086/106] ccs-pll: Separate VT divisor limit calculation from the rest [v2,087/106] ccs-pll: Add trivial dual PLL support [v2,088/106] ccs: Dual PLL support [v2,089/106] ccs-pll: Add support for DDR OP system and pixel clocks [v2,090/106] ccs: Add support for DDR OP SYS and OP PIX clocks [v2,091/106] ccs: Print written register values [v2,092/106] ccs-pll: Print pixel rates [v2,093/106] ccs: Add support for obtaining C-PHY configuration from firmware [v2,094/106] ccs: Add digital gain support [v2,095/106] ccs: Add support for old-style SMIA digital gain [v2,096/106] ccs: Remove analogue gain field [v2,097/106] ccs: Only add analogue gain control if the device supports it [v2,098/106] v4l: uapi: Add user control base for CCS controls [v2,099/106] v4l: uapi: ccs: Add controls for analogue gain constants [v2,100/106] ccs: Add support for analogue gain coefficient controls [v2,101/106] v4l: uapi: ccs: Add controls for CCS alternative analogue gain [v2,102/106] ccs: Add support for alternate analogue global gain [v2,103/106] ccs: Add debug prints for MSR registers [v2,104/106] v4l: uapi: ccs: Add CCS controls for shading correction [v2,105/106] ccs: Add shading correction and luminance correction level controls [v2,106/106] ccs: Add CCS ACPI device ID

Message ID

20201007084557.25843-62-sakari.ailus@linux.intel.com (mailing list archive)

State

New, archived

Headers

From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Subject: [PATCH v2 071/106] ccs-pll: Add support for lane speed model
Date: Wed,  7 Oct 2020 11:45:22 +0300
Message-Id: <20201007084557.25843-62-sakari.ailus@linux.intel.com>
In-Reply-To: <20201007084557.25843-1-sakari.ailus@linux.intel.com>
References: <20201007084505.25761-1-sakari.ailus@linux.intel.com>
 <20201007084557.25843-1-sakari.ailus@linux.intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

CCS driver | expand

Commit Message

Sakari Ailus Oct. 7, 2020, 8:45 a.m. UTC

CCS PLL includes a capability to calculate the VT clocks on per-lane
basis. Add support for this feature.

Move calculation of the pixel rate on the CSI-2 bus early in the function
as everything needed to calculate it is already available.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 drivers/media/i2c/ccs-pll.c | 36 +++++++++++++++++++++++++-----------
 drivers/media/i2c/ccs-pll.h |  6 ++++++
 2 files changed, 31 insertions(+), 11 deletions(-)

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index d33a2575329c..9750b49d834a 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -251,11 +251,12 @@  __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 	op_pll_fr->pll_op_clk_freq_hz = op_pll_fr->pll_ip_clk_freq_hz
 		* op_pll_fr->pll_multiplier;
 
-	op_pll_bk->pix_clk_div = pll->bits_per_pixel;
-	dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
-
+	op_pll_bk->pix_clk_div = pll->bits_per_pixel
+		* pll->op_lanes / pll->csi2.lanes;
 	op_pll_bk->pix_clk_freq_hz =
 		op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div;
+	dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll_bk->pix_clk_div);
+
 
 	if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
 		/* No OP clocks --- VT clocks are used instead. */
@@ -283,15 +284,16 @@  __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 	 * divisors. One must make sure that horizontal blanking is
 	 * enough to accommodate the CSI-2 sync codes.
 	 *
-	 * Take scaling factor into account as well.
+	 * Take scaling factor and number of VT lanes into account as well.
 	 *
 	 * Find absolute limits for the factor of vt divider.
 	 */
 	dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
 	min_vt_div = DIV_ROUND_UP(op_pll_bk->pix_clk_div
-				  * op_pll_bk->sys_clk_div * pll->scale_n,
-				  lane_op_clock_ratio * vt_op_binning_div
-				  * pll->scale_m);
+				  * op_pll_bk->sys_clk_div * pll->scale_n
+				  * pll->vt_lanes,
+				  pll->op_lanes * vt_op_binning_div
+				  * pll->scale_m * lane_op_clock_ratio);
 
 	/* Find smallest and biggest allowed vt divisor. */
 	dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
@@ -387,9 +389,8 @@  __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 		pll->vt_bk.sys_clk_freq_hz / pll->vt_bk.pix_clk_div;
 
 out_skip_vt_calc:
-	pll->pixel_rate_csi =
-		op_pll_bk->pix_clk_freq_hz * lane_op_clock_ratio;
-	pll->pixel_rate_pixel_array = pll->vt_bk.pix_clk_freq_hz;
+	pll->pixel_rate_pixel_array =
+		pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
 
 	return check_all_bounds(dev, lim, op_lim_fr, op_lim_bk, pll, op_pll_fr,
 				op_pll_bk);
@@ -409,6 +410,13 @@  int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 	uint32_t i;
 	int rval = -EINVAL;
 
+	if (!(pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL)) {
+		pll->op_lanes = 1;
+		pll->vt_lanes = 1;
+	}
+	dev_dbg(dev, "vt_lanes: %u\n", pll->vt_lanes);
+	dev_dbg(dev, "op_lanes: %u\n", pll->op_lanes);
+
 	if (pll->flags & CCS_PLL_FLAG_NO_OP_CLOCKS) {
 		/*
 		 * If there's no OP PLL at all, use the VT values
@@ -433,12 +441,18 @@  int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 	case CCS_PLL_BUS_TYPE_CSI2_DPHY:
 		/* CSI transfers 2 bits per clock per lane; thus times 2 */
 		op_pll_bk->sys_clk_freq_hz = pll->link_freq * 2
-			* (pll->csi2.lanes / lane_op_clock_ratio);
+			* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+			   1 : pll->csi2.lanes) / lane_op_clock_ratio;
 		break;
 	default:
 		return -EINVAL;
 	}
 
+	pll->pixel_rate_csi =
+		op_pll_bk->pix_clk_freq_hz
+		* (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+		   pll->csi2.lanes : 1) * lane_op_clock_ratio;
+
 	/* Figure out limits for OP pre-pll divider based on extclk */
 	dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n",
 		op_lim_fr->min_pre_pll_clk_div, op_lim_fr->max_pre_pll_clk_div);
diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index f772ed8ef579..57308b8f3a8a 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -22,6 +22,8 @@ 
 /* op pix clock is for all lanes in total normally */
 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE			BIT(0)
 #define CCS_PLL_FLAG_NO_OP_CLOCKS				BIT(1)
+/* CCS PLL flags */
+#define CCS_PLL_FLAG_LANE_SPEED_MODEL				BIT(2)
 
 /**
  * struct ccs_pll_branch_fr - CCS PLL configuration (front)
@@ -63,6 +65,8 @@  struct ccs_pll_branch_bk {
  * All information required to calculate CCS PLL configuration.
  *
  * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)
+ * @op_lanes: Number of operational lanes (input)
+ * @vt_lanes: Number of video timing lanes (input)
  * @csi2.lanes: The number of the CSI-2 data lanes (input)
  * @binning_vertical: Vertical binning factor (input)
  * @binning_horizontal: Horizontal binning factor (input)
@@ -83,6 +87,8 @@  struct ccs_pll_branch_bk {
 struct ccs_pll {
 	/* input values */
 	uint8_t bus_type;
+	uint8_t op_lanes;
+	uint8_t vt_lanes;
 	struct {
 		uint8_t lanes;
 	} csi2;

[v2,071/106] ccs-pll: Add support for lane speed model

Commit Message

Patch