diff mbox series

[v3,06/12] dt-bindings: arm: mediatek: add definition for mt8195 mmsys

Message ID 20210715173750.10852-7-jason-jh.lin@mediatek.com (mailing list archive)
State New, archived
Headers show
Series Add MediaTek SoC DRM (vdosys0) support for mt8195 | expand

Commit Message

Jason-JH.Lin July 15, 2021, 5:37 p.m. UTC 
There are 2 display hardware path in mt8195, namely vdosys0 and
vdosys1, so add their definition in mtk-mmsys documentation.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index ea31c7c2792c..e6cd6e2173d4 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -66,6 +66,16 @@  properties:
               - mediatek,mt8192-mmsys
           - enum:
               - syscon
+      - items:
+          - enum:
+              - mediatek,mt8195-vdosys0
+          - enum:
+              - syscon
+      - items:
+          - enum:
+              - mediatek,mt8195-vdosys1
+          - enum:
+              - syscon
 
   reg:
     maxItems: 1
@@ -99,4 +109,18 @@  examples:
         #clock-cells = <1>;
     };
 
+    vdosys0: syscon@1c01a000 {
+        compatible = "mediatek,mt8195-vdosys0", "syscon";
+        reg = <0 0x1c01a000 0 0x1000>;
+        #clock-cells = <1>;
+        mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
+    };
+
+    vdosys1: syscon@1c100000 {
+        compatible = "mediatek,mt8195-vdosys1", "syscon";
+        reg = <0 0x1c100000 0 0x1000>;
+        #clock-cells = <1>;
+        mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+    };
+
 ...