| Message ID | 20211129184439.16892-11-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年11月30日 週二 上午2:44寫道： > > Remove the unsed define in mtk_drm_ddp_comp.c Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 ---------- > 1 file changed, 10 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 3704e4b7f3c5..7d3bd6214c15 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -21,8 +21,6 @@ > #include "mtk_drm_crtc.h" > > #define DISP_OD_EN 0x0000 > -#define DISP_OD_INTEN 0x0008 > -#define DISP_OD_INTSTA 0x000c > #define DISP_OD_CFG 0x0020 > #define DISP_OD_SIZE 0x0030 > #define DISP_DITHER_5 0x0114 > @@ -39,26 +37,18 @@ > #define DITHER_ENGINE_EN BIT(1) > #define DISP_DITHER_SIZE 0x0030 > > -#define LUT_10BIT_MASK 0x03ff > - > #define OD_RELAYMODE BIT(0) > > #define UFO_BYPASS BIT(2) > > #define DISP_DITHERING BIT(2) > #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) > -#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) > #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) > -#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16) > #define DITHER_NEW_BIT_MODE BIT(0) > #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) > -#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24) > #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) > -#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16) > #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) > -#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8) > #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) > -#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) > > #define DISP_POSTMASK_EN 0x0000 > #define POSTMASK_EN BIT(0) > -- > 2.18.0 >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 3704e4b7f3c5..7d3bd6214c15 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -21,8 +21,6 @@ #include "mtk_drm_crtc.h" #define DISP_OD_EN 0x0000 -#define DISP_OD_INTEN 0x0008 -#define DISP_OD_INTSTA 0x000c #define DISP_OD_CFG 0x0020 #define DISP_OD_SIZE 0x0030 #define DISP_DITHER_5 0x0114 @@ -39,26 +37,18 @@ #define DITHER_ENGINE_EN BIT(1) #define DISP_DITHER_SIZE 0x0030 -#define LUT_10BIT_MASK 0x03ff - #define OD_RELAYMODE BIT(0) #define UFO_BYPASS BIT(2) #define DISP_DITHERING BIT(2) #define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28) -#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24) #define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20) -#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16) #define DITHER_NEW_BIT_MODE BIT(0) #define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28) -#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24) #define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20) -#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16) #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) -#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) -#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0) #define DISP_POSTMASK_EN 0x0000 #define POSTMASK_EN BIT(0)