| Message ID | 20211129184439.16892-12-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Mediatek Soc DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年11月30日 週二 上午2:44寫道： > > Add DISP_REG prefix for the define of register offset to > make the difference from the define of register value. Applied to mediatek-drm-next [1], thanks. [1] https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next Regards, Chun-Kuang. > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> > --- > rebase on series [1] > > [1] drm/mediatek: add support for mediatek SOC MT8192 > - https://patchwork.kernel.org/project/linux-mediatek/list/?series=529489 > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 62 +++++++++++---------- > 1 file changed, 32 insertions(+), 30 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 7d3bd6214c15..40ea57fc4473 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -20,22 +20,22 @@ > #include "mtk_drm_ddp_comp.h" > #include "mtk_drm_crtc.h" > > -#define DISP_OD_EN 0x0000 > -#define DISP_OD_CFG 0x0020 > -#define DISP_OD_SIZE 0x0030 > -#define DISP_DITHER_5 0x0114 > -#define DISP_DITHER_7 0x011c > -#define DISP_DITHER_15 0x013c > -#define DISP_DITHER_16 0x0140 > +#define DISP_REG_OD_EN 0x0000 > +#define DISP_REG_OD_CFG 0x0020 > +#define DISP_REG_OD_SIZE 0x0030 > +#define DISP_REG_DITHER_5 0x0114 > +#define DISP_REG_DITHER_7 0x011c > +#define DISP_REG_DITHER_15 0x013c > +#define DISP_REG_DITHER_16 0x0140 > > #define DISP_REG_UFO_START 0x0000 > > -#define DISP_DITHER_EN 0x0000 > +#define DISP_REG_DITHER_EN 0x0000 > #define DITHER_EN BIT(0) > -#define DISP_DITHER_CFG 0x0020 > +#define DISP_REG_DITHER_CFG 0x0020 > #define DITHER_RELAY_MODE BIT(0) > #define DITHER_ENGINE_EN BIT(1) > -#define DISP_DITHER_SIZE 0x0030 > +#define DISP_REG_DITHER_SIZE 0x0030 > > #define OD_RELAYMODE BIT(0) > > @@ -50,11 +50,11 @@ > #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) > #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) > > -#define DISP_POSTMASK_EN 0x0000 > +#define DISP_REG_POSTMASK_EN 0x0000 > #define POSTMASK_EN BIT(0) > -#define DISP_POSTMASK_CFG 0x0020 > +#define DISP_REG_POSTMASK_CFG 0x0020 > #define POSTMASK_RELAY_MODE BIT(0) > -#define DISP_POSTMASK_SIZE 0x0030 > +#define DISP_REG_POSTMASK_SIZE 0x0030 > > struct mtk_ddp_comp_dev { > struct clk *clk; > @@ -130,19 +130,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, > return; > > if (bpc >= MTK_MIN_BPC) { > - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); > - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); > + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); > mtk_ddp_write(cmdq_pkt, > DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | > DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | > DITHER_NEW_BIT_MODE, > - cmdq_reg, regs, DISP_DITHER_15); > + cmdq_reg, regs, DISP_REG_DITHER_15); > mtk_ddp_write(cmdq_pkt, > DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | > DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | > DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | > DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), > - cmdq_reg, regs, DISP_DITHER_16); > + cmdq_reg, regs, DISP_REG_DITHER_16); > mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); > } > } > @@ -162,16 +162,16 @@ static void mtk_od_config(struct device *dev, unsigned int w, > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE); > - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG); > - mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt); > + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); > + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); > + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt); > } > > static void mtk_od_start(struct device *dev) > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - writel(1, priv->regs + DISP_OD_EN); > + writel(1, priv->regs + DISP_REG_OD_EN); > } > > static void mtk_ufoe_start(struct device *dev) > @@ -187,9 +187,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w, > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); > - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); > - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG, > + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, > + DISP_REG_DITHER_SIZE); > + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, > + DISP_REG_DITHER_CFG); > + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG, > DITHER_ENGINE_EN, cmdq_pkt); > } > > @@ -197,14 +199,14 @@ static void mtk_dither_start(struct device *dev) > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - writel(DITHER_EN, priv->regs + DISP_DITHER_EN); > + writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN); > } > > static void mtk_dither_stop(struct device *dev) > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - writel_relaxed(0x0, priv->regs + DISP_DITHER_EN); > + writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN); > } > > static void mtk_postmask_config(struct device *dev, unsigned int w, > @@ -214,23 +216,23 @@ static void mtk_postmask_config(struct device *dev, unsigned int w, > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, > - DISP_POSTMASK_SIZE); > + DISP_REG_POSTMASK_SIZE); > mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, > - priv->regs, DISP_POSTMASK_CFG); > + priv->regs, DISP_REG_POSTMASK_CFG); > } > > static void mtk_postmask_start(struct device *dev) > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); > + writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN); > } > > static void mtk_postmask_stop(struct device *dev) > { > struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); > > - writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); > + writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN); > } > > static const struct mtk_ddp_comp_funcs ddp_aal = { > -- > 2.18.0 >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 7d3bd6214c15..40ea57fc4473 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -20,22 +20,22 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_crtc.h" -#define DISP_OD_EN 0x0000 -#define DISP_OD_CFG 0x0020 -#define DISP_OD_SIZE 0x0030 -#define DISP_DITHER_5 0x0114 -#define DISP_DITHER_7 0x011c -#define DISP_DITHER_15 0x013c -#define DISP_DITHER_16 0x0140 +#define DISP_REG_OD_EN 0x0000 +#define DISP_REG_OD_CFG 0x0020 +#define DISP_REG_OD_SIZE 0x0030 +#define DISP_REG_DITHER_5 0x0114 +#define DISP_REG_DITHER_7 0x011c +#define DISP_REG_DITHER_15 0x013c +#define DISP_REG_DITHER_16 0x0140 #define DISP_REG_UFO_START 0x0000 -#define DISP_DITHER_EN 0x0000 +#define DISP_REG_DITHER_EN 0x0000 #define DITHER_EN BIT(0) -#define DISP_DITHER_CFG 0x0020 +#define DISP_REG_DITHER_CFG 0x0020 #define DITHER_RELAY_MODE BIT(0) #define DITHER_ENGINE_EN BIT(1) -#define DISP_DITHER_SIZE 0x0030 +#define DISP_REG_DITHER_SIZE 0x0030 #define OD_RELAYMODE BIT(0) @@ -50,11 +50,11 @@ #define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12) #define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4) -#define DISP_POSTMASK_EN 0x0000 +#define DISP_REG_POSTMASK_EN 0x0000 #define POSTMASK_EN BIT(0) -#define DISP_POSTMASK_CFG 0x0020 +#define DISP_REG_POSTMASK_CFG 0x0020 #define POSTMASK_RELAY_MODE BIT(0) -#define DISP_POSTMASK_SIZE 0x0030 +#define DISP_REG_POSTMASK_SIZE 0x0030 struct mtk_ddp_comp_dev { struct clk *clk; @@ -130,19 +130,19 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg, return; if (bpc >= MTK_MIN_BPC) { - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_5); - mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_DITHER_7); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_5); + mtk_ddp_write(cmdq_pkt, 0, cmdq_reg, regs, DISP_REG_DITHER_7); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) | DITHER_NEW_BIT_MODE, - cmdq_reg, regs, DISP_DITHER_15); + cmdq_reg, regs, DISP_REG_DITHER_15); mtk_ddp_write(cmdq_pkt, DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) | DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) | DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc), - cmdq_reg, regs, DISP_DITHER_16); + cmdq_reg, regs, DISP_REG_DITHER_16); mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg); } } @@ -162,16 +162,16 @@ static void mtk_od_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_OD_SIZE); - mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_OD_CFG); - mtk_dither_set(dev, bpc, DISP_OD_CFG, cmdq_pkt); + mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, DISP_REG_OD_SIZE); + mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, &priv->cmdq_reg, priv->regs, DISP_REG_OD_CFG); + mtk_dither_set(dev, bpc, DISP_REG_OD_CFG, cmdq_pkt); } static void mtk_od_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel(1, priv->regs + DISP_OD_EN); + writel(1, priv->regs + DISP_REG_OD_EN); } static void mtk_ufoe_start(struct device *dev) @@ -187,9 +187,11 @@ static void mtk_dither_config(struct device *dev, unsigned int w, { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE); - mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG); - mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG, + mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, + DISP_REG_DITHER_SIZE); + mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, + DISP_REG_DITHER_CFG); + mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_REG_DITHER_CFG, DITHER_ENGINE_EN, cmdq_pkt); } @@ -197,14 +199,14 @@ static void mtk_dither_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel(DITHER_EN, priv->regs + DISP_DITHER_EN); + writel(DITHER_EN, priv->regs + DISP_REG_DITHER_EN); } static void mtk_dither_stop(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel_relaxed(0x0, priv->regs + DISP_DITHER_EN); + writel_relaxed(0x0, priv->regs + DISP_REG_DITHER_EN); } static void mtk_postmask_config(struct device *dev, unsigned int w, @@ -214,23 +216,23 @@ static void mtk_postmask_config(struct device *dev, unsigned int w, struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs, - DISP_POSTMASK_SIZE); + DISP_REG_POSTMASK_SIZE); mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg, - priv->regs, DISP_POSTMASK_CFG); + priv->regs, DISP_REG_POSTMASK_CFG); } static void mtk_postmask_start(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel(POSTMASK_EN, priv->regs + DISP_POSTMASK_EN); + writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN); } static void mtk_postmask_stop(struct device *dev) { struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev); - writel_relaxed(0x0, priv->regs + DISP_POSTMASK_EN); + writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN); } static const struct mtk_ddp_comp_funcs ddp_aal = {