| Message ID | 20220609104001.97753-3-angelogioacchino.delregno@collabora.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | MediaTek Helio X10 MT6795 - M4U/IOMMU Support | expand |
On Thu, 2022-06-09 at 12:40 +0200, AngeloGioacchino Del Regno wrote: > In preparation for adding support for MT6795, add a new flag named > TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat > type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat > checks there in the future. > > Signed-off-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> Retitle to: iommu/mediatek: Xxx, then Reviewed-by: Yong Wu <yong.wu@mediatek.com> > --- > drivers/iommu/mtk_iommu.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c > index 0ea0848581e9..8611cf8e4bd5 100644 > --- a/drivers/iommu/mtk_iommu.c > +++ b/drivers/iommu/mtk_iommu.c > @@ -140,6 +140,7 @@ > #define IFA_IOMMU_PCIE_SUPPORT BIT(16) > /* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ > #define HAS_PERI_IOMMU1_REG BIT(17) > +#define TF_PORT_TO_ADDR_MT8173 BIT(18) > > #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ > ((((pdata)->flags) & (mask)) == (_x)) > @@ -960,7 +961,7 @@ static int mtk_iommu_hw_init(const struct > mtk_iommu_data *data, unsigned int ban > * Global control settings are in bank0. May re-init these > global registers > * since no sure if there is bank0 consumers. > */ > - if (data->plat_data->m4u_plat == M4U_MT8173) { > + if (MTK_IOMMU_HAS_FLAG(data->plat_data, > TF_PORT_TO_ADDR_MT8173)) { > regval = F_MMU_PREFETCH_RT_REPLACE_MOD | > F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; > } else { > @@ -1437,7 +1438,8 @@ static const struct mtk_iommu_plat_data > mt8167_data = { > static const struct mtk_iommu_plat_data mt8173_data = { > .m4u_plat = M4U_MT8173, > .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | > - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, > + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | > + TF_PORT_TO_ADDR_MT8173, > .inv_sel_reg = REG_MMU_INV_SEL_GEN1, > .banks_num = 1, > .banks_enable = {true},
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c index 0ea0848581e9..8611cf8e4bd5 100644 --- a/drivers/iommu/mtk_iommu.c +++ b/drivers/iommu/mtk_iommu.c @@ -140,6 +140,7 @@ #define IFA_IOMMU_PCIE_SUPPORT BIT(16) /* IOMMU I/O (r/w) is enabled using PERICFG_IOMMU_1 register */ #define HAS_PERI_IOMMU1_REG BIT(17) +#define TF_PORT_TO_ADDR_MT8173 BIT(18) #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \ ((((pdata)->flags) & (mask)) == (_x)) @@ -960,7 +961,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data, unsigned int ban * Global control settings are in bank0. May re-init these global registers * since no sure if there is bank0 consumers. */ - if (data->plat_data->m4u_plat == M4U_MT8173) { + if (MTK_IOMMU_HAS_FLAG(data->plat_data, TF_PORT_TO_ADDR_MT8173)) { regval = F_MMU_PREFETCH_RT_REPLACE_MOD | F_MMU_TF_PROT_TO_PROGRAM_ADDR_MT8173; } else { @@ -1437,7 +1438,8 @@ static const struct mtk_iommu_plat_data mt8167_data = { static const struct mtk_iommu_plat_data mt8173_data = { .m4u_plat = M4U_MT8173, .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | - HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | + TF_PORT_TO_ADDR_MT8173, .inv_sel_reg = REG_MMU_INV_SEL_GEN1, .banks_num = 1, .banks_enable = {true},
In preparation for adding support for MT6795, add a new flag named TF_PORT_TO_ADDR_MT8173 and use that instead of checking for m4u_plat type in mtk_iommu_hw_init() to avoid seeing a long list of m4u_plat checks there in the future. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> --- drivers/iommu/mtk_iommu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)