Message ID | 20220613064841.10481-2-rex-bc.chen@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/mediatek: Add MT8195 dp_intf driver | expand |
On Mon, 13 Jun 2022 14:48:30 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > DP_INTF is similar to DPI but does not have the exact same feature set > or register layouts. > > DP_INTF is the sink of the display pipeline that is connected to the > DisplayPort controller and encoder unit. It takes the same clocks as > DPI. > > In this patch, we also do these string replacement: > - s/mediatek/MediaTek/ in title. > - s/Mediatek/MediaTek/ in description. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.example.dtb: dpi@1401d000: clocks: [[4294967295, 40], [4294967295, 41], [4294967295, 8]] is too short From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.example.dtb: dpi@1401d000: clock-names: ['pixel', 'engine', 'pll'] is too short From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Hi, Bo-Chen: On Mon, 2022-06-13 at 14:48 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > DP_INTF is similar to DPI but does not have the exact same feature > set > or register layouts. > > DP_INTF is the sink of the display pipeline that is connected to the > DisplayPort controller and encoder unit. It takes the same clocks as > DPI. > > In this patch, we also do these string replacement: > - s/mediatek/MediaTek/ in title. > - s/Mediatek/MediaTek/ in description. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++--- > -- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > index 77ee1b923991..ca1b48e78581 100644 > --- > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > +++ > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yam > l > @@ -4,16 +4,16 @@ > $id: > http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: mediatek DPI Controller Device Tree Bindings > +title: MediaTek DPI and DP_INTF Controller > > maintainers: > - CK Hu <ck.hu@mediatek.com> > - Jitao shi <jitao.shi@mediatek.com> > > description: | > - The Mediatek DPI function block is a sink of the display subsystem > and > - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a > parallel > - output bus. > + The MediaTek DPI and DP_INTF function blocks are a sink of the > display > + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 > pixel data on a > + parallel output bus. > > properties: > compatible: > @@ -24,6 +24,7 @@ properties: > - mediatek,mt8183-dpi > - mediatek,mt8186-dpi > - mediatek,mt8192-dpi > + - mediatek,mt8195-dp_intf > > reg: > maxItems: 1 > @@ -36,12 +37,14 @@ properties: > - description: Pixel Clock > - description: Engine Clock > - description: DPI PLL > + - description: Clock gate for PLL Why DP_INTF has this additional clock? What is the new hardware block (compared with DPI) need this clock? Why this is different than DPI? Regards, CK > > clock-names: > items: > - const: pixel > - const: engine > - const: pll > + - const: pll_gate > > pinctrl-0: true > pinctrl-1: true > @@ -55,7 +58,7 @@ properties: > $ref: /schemas/graph.yaml#/properties/port > description: > Output port node. This port should be connected to the input > port of an > - attached HDMI or LVDS encoder chip. > + attached HDMI, LVDS or DisplayPort encoder chip. > > required: > - compatible
On Mon, Jun 13, 2022 at 02:48:30PM +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > DP_INTF is similar to DPI but does not have the exact same feature set > or register layouts. > > DP_INTF is the sink of the display pipeline that is connected to the > DisplayPort controller and encoder unit. It takes the same clocks as > DPI. > > In this patch, we also do these string replacement: > - s/mediatek/MediaTek/ in title. > - s/Mediatek/MediaTek/ in description. > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- > .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > index 77ee1b923991..ca1b48e78581 100644 > --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml > @@ -4,16 +4,16 @@ > $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# > $schema: http://devicetree.org/meta-schemas/core.yaml# > > -title: mediatek DPI Controller Device Tree Bindings > +title: MediaTek DPI and DP_INTF Controller > > maintainers: > - CK Hu <ck.hu@mediatek.com> > - Jitao shi <jitao.shi@mediatek.com> > > description: | > - The Mediatek DPI function block is a sink of the display subsystem and > - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel > - output bus. > + The MediaTek DPI and DP_INTF function blocks are a sink of the display > + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a > + parallel output bus. > > properties: > compatible: > @@ -24,6 +24,7 @@ properties: > - mediatek,mt8183-dpi > - mediatek,mt8186-dpi > - mediatek,mt8192-dpi > + - mediatek,mt8195-dp_intf > > reg: > maxItems: 1 > @@ -36,12 +37,14 @@ properties: > - description: Pixel Clock > - description: Engine Clock > - description: DPI PLL > + - description: Clock gate for PLL > > clock-names: > items: > - const: pixel > - const: engine > - const: pll > + - const: pll_gate You just added a new required clock for everyone. > > pinctrl-0: true > pinctrl-1: true > @@ -55,7 +58,7 @@ properties: > $ref: /schemas/graph.yaml#/properties/port > description: > Output port node. This port should be connected to the input port of an > - attached HDMI or LVDS encoder chip. > + attached HDMI, LVDS or DisplayPort encoder chip. > > required: > - compatible > -- > 2.18.0 > >
On Tue, 2022-06-14 at 14:24 -0600, Rob Herring wrote: > On Mon, Jun 13, 2022 at 02:48:30PM +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > DP_INTF is similar to DPI but does not have the exact same feature > > set > > or register layouts. > > > > DP_INTF is the sink of the display pipeline that is connected to > > the > > DisplayPort controller and encoder unit. It takes the same clocks > > as > > DPI. > > > > In this patch, we also do these string replacement: > > - s/mediatek/MediaTek/ in title. > > - s/Mediatek/MediaTek/ in description. > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++- > > ---- > > 1 file changed, 8 insertions(+), 5 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > aml > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > aml > > index 77ee1b923991..ca1b48e78581 100644 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > aml > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > aml > > @@ -4,16 +4,16 @@ > > $id: > > https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml*__;Iw!!CTRNKA9wMg0ARbw!0wzvKisC8j2vSMbYtNhgV1niXflyQgVHmgSPCVo94UQV-GiFqhMtdoowjpgIYMXH8wDn$ > > > > $schema: > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0wzvKisC8j2vSMbYtNhgV1niXflyQgVHmgSPCVo94UQV-GiFqhMtdoowjpgIYEfMUrSk$ > > > > > > -title: mediatek DPI Controller Device Tree Bindings > > +title: MediaTek DPI and DP_INTF Controller > > > > maintainers: > > - CK Hu <ck.hu@mediatek.com> > > - Jitao shi <jitao.shi@mediatek.com> > > > > description: | > > - The Mediatek DPI function block is a sink of the display > > subsystem and > > - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a > > parallel > > - output bus. > > + The MediaTek DPI and DP_INTF function blocks are a sink of the > > display > > + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 > > pixel data on a > > + parallel output bus. > > > > properties: > > compatible: > > @@ -24,6 +24,7 @@ properties: > > - mediatek,mt8183-dpi > > - mediatek,mt8186-dpi > > - mediatek,mt8192-dpi > > + - mediatek,mt8195-dp_intf > > > > reg: > > maxItems: 1 > > @@ -36,12 +37,14 @@ properties: > > - description: Pixel Clock > > - description: Engine Clock > > - description: DPI PLL > > + - description: Clock gate for PLL > > > > clock-names: > > items: > > - const: pixel > > - const: engine > > - const: pll > > + - const: pll_gate > > You just added a new required clock for everyone. > Hello Rob, We can remove this clock and using clock framework to enable this pll gate, so I will remove this in next version. BRs, Bo-Chen > > > > pinctrl-0: true > > pinctrl-1: true > > @@ -55,7 +58,7 @@ properties: > > $ref: /schemas/graph.yaml#/properties/port > > description: > > Output port node. This port should be connected to the input > > port of an > > - attached HDMI or LVDS encoder chip. > > + attached HDMI, LVDS or DisplayPort encoder chip. > > > > required: > > - compatible > > -- > > 2.18.0 > > > >
On Tue, 2022-06-14 at 11:05 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Mon, 2022-06-13 at 14:48 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > DP_INTF is similar to DPI but does not have the exact same feature > > set > > or register layouts. > > > > DP_INTF is the sink of the display pipeline that is connected to > > the > > DisplayPort controller and encoder unit. It takes the same clocks > > as > > DPI. > > > > In this patch, we also do these string replacement: > > - s/mediatek/MediaTek/ in title. > > - s/Mediatek/MediaTek/ in description. > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > .../bindings/display/mediatek/mediatek,dpi.yaml | 13 ++++++++- > > -- > > -- > > 1 file changed, 8 insertions(+), 5 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > am > > l > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > am > > l > > index 77ee1b923991..ca1b48e78581 100644 > > --- > > a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > am > > l > > +++ > > b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.y > > am > > l > > @@ -4,16 +4,16 @@ > > $id: > > http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# > > $schema: http://devicetree.org/meta-schemas/core.yaml# > > > > -title: mediatek DPI Controller Device Tree Bindings > > +title: MediaTek DPI and DP_INTF Controller > > > > maintainers: > > - CK Hu <ck.hu@mediatek.com> > > - Jitao shi <jitao.shi@mediatek.com> > > > > description: | > > - The Mediatek DPI function block is a sink of the display > > subsystem > > and > > - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a > > parallel > > - output bus. > > + The MediaTek DPI and DP_INTF function blocks are a sink of the > > display > > + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 > > pixel data on a > > + parallel output bus. > > > > properties: > > compatible: > > @@ -24,6 +24,7 @@ properties: > > - mediatek,mt8183-dpi > > - mediatek,mt8186-dpi > > - mediatek,mt8192-dpi > > + - mediatek,mt8195-dp_intf > > > > reg: > > maxItems: 1 > > @@ -36,12 +37,14 @@ properties: > > - description: Pixel Clock > > - description: Engine Clock > > - description: DPI PLL > > + - description: Clock gate for PLL > > Why DP_INTF has this additional clock? What is the new hardware block > (compared with DPI) need this clock? Why this is different than DPI? > > Regards, > CK > Hello CK, as previous reply, I will remove this clock. BRs, Bo-Chen > > > > clock-names: > > items: > > - const: pixel > > - const: engine > > - const: pll > > + - const: pll_gate > > > > pinctrl-0: true > > pinctrl-1: true > > @@ -55,7 +58,7 @@ properties: > > $ref: /schemas/graph.yaml#/properties/port > > description: > > Output port node. This port should be connected to the input > > port of an > > - attached HDMI or LVDS encoder chip. > > + attached HDMI, LVDS or DisplayPort encoder chip. > > > > required: > > - compatible > >
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index 77ee1b923991..ca1b48e78581 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -4,16 +4,16 @@ $id: http://devicetree.org/schemas/display/mediatek/mediatek,dpi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: mediatek DPI Controller Device Tree Bindings +title: MediaTek DPI and DP_INTF Controller maintainers: - CK Hu <ck.hu@mediatek.com> - Jitao shi <jitao.shi@mediatek.com> description: | - The Mediatek DPI function block is a sink of the display subsystem and - provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel - output bus. + The MediaTek DPI and DP_INTF function blocks are a sink of the display + subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a + parallel output bus. properties: compatible: @@ -24,6 +24,7 @@ properties: - mediatek,mt8183-dpi - mediatek,mt8186-dpi - mediatek,mt8192-dpi + - mediatek,mt8195-dp_intf reg: maxItems: 1 @@ -36,12 +37,14 @@ properties: - description: Pixel Clock - description: Engine Clock - description: DPI PLL + - description: Clock gate for PLL clock-names: items: - const: pixel - const: engine - const: pll + - const: pll_gate pinctrl-0: true pinctrl-1: true @@ -55,7 +58,7 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Output port node. This port should be connected to the input port of an - attached HDMI or LVDS encoder chip. + attached HDMI, LVDS or DisplayPort encoder chip. required: - compatible