| Message ID | 20221106085034.12582-5-linux@fw-web.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add BananaPi R3 | expand |
On 06/11/2022 09:50, Frank Wunderlich wrote: > From: Sam Shih <sam.shih@mediatek.com> > > This patch adds crypto engine support for MT7986. > > Signed-off-by: Vic Wu <vic.wu@mediatek.com> > Signed-off-by: Sam Shih <sam.shih@mediatek.com> > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Applied, thanks! > --- > arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts | 4 ++++ > arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 15 +++++++++++++++ > arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts | 4 ++++ > 3 files changed, 23 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > index de5d771e5251..2b5d7ea31b4d 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts > @@ -43,6 +43,10 @@ reg_5v: regulator-5v { > }; > }; > > +&crypto { > + status = "okay"; > +}; > + > ð { > status = "okay"; > > diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > index 58bbecfbab98..1c7a973c28ca 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi > @@ -205,6 +205,21 @@ trng: rng@1020f000 { > status = "disabled"; > }; > > + crypto: crypto@10320000 { > + compatible = "inside-secure,safexcel-eip97"; > + reg = <0 0x10320000 0 0x40000>; > + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "ring0", "ring1", "ring2", "ring3"; > + clocks = <&infracfg CLK_INFRA_EIP97_CK>; > + clock-names = "infra_eip97_ck"; > + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; > + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; > + status = "disabled"; > + }; > + > uart0: serial@11002000 { > compatible = "mediatek,mt7986-uart", > "mediatek,mt6577-uart"; > diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts > index cd1763fa7f19..a98025112b5a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts > +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts > @@ -43,6 +43,10 @@ reg_5v: regulator-5v { > }; > }; > > +&crypto { > + status = "okay"; > +}; > + > ð { > status = "okay"; >
diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts index de5d771e5251..2b5d7ea31b4d 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts @@ -43,6 +43,10 @@ reg_5v: regulator-5v { }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 58bbecfbab98..1c7a973c28ca 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -205,6 +205,21 @@ trng: rng@1020f000 { status = "disabled"; }; + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&infracfg CLK_INFRA_EIP97_CK>; + clock-names = "infra_eip97_ck"; + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; + status = "disabled"; + }; + uart0: serial@11002000 { compatible = "mediatek,mt7986-uart", "mediatek,mt6577-uart"; diff --git a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index cd1763fa7f19..a98025112b5a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -43,6 +43,10 @@ reg_5v: regulator-5v { }; }; +&crypto { + status = "okay"; +}; + ð { status = "okay";