| Message ID | 20231023-display-support-v1-11-5c860ed5c33b@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add display support for the MT8365-EVK board | expand |
Yo, On Mon, Oct 23, 2023 at 04:40:11PM +0200, Alexandre Mergnat wrote: > According to the Mediatek datasheet, the display PWM block has a power > domain. Datasheet for which soc? The mt8173? Is it valid for all devices in this binding? Cheers, Conor. > > Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> > --- > Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > index 153e146df7d4..efe0cacf55b7 100644 > --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml > @@ -53,6 +53,12 @@ properties: > - const: main > - const: mm > > + power-domains: > + maxItems: 1 > + description: A phandle and PM domain specifier as defined by bindings of > + the power controller specified by phandle. See > + Documentation/devicetree/bindings/power/power-domain.yaml for details. > + > required: > - compatible > - reg > @@ -67,6 +73,7 @@ examples: > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/clock/mt8173-clk.h> > #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mt8173-power.h> > > pwm0: pwm@1401e000 { > compatible = "mediatek,mt8173-disp-pwm"; > @@ -75,4 +82,5 @@ examples: > clocks = <&mmsys CLK_MM_DISP_PWM026M>, > <&mmsys CLK_MM_DISP_PWM0MM>; > clock-names = "main", "mm"; > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > }; > > -- > 2.25.1 >
Hello Conor On 23/10/2023 19:38, Conor Dooley wrote: > Yo, > > On Mon, Oct 23, 2023 at 04:40:11PM +0200, Alexandre Mergnat wrote: >> According to the Mediatek datasheet, the display PWM block has a power >> domain. > > Datasheet for which soc? The mt8173? Is it valid for all devices in this > binding? I can't verify for other SoC. Then, I fix the commit message and remove the example changes. > > Cheers, > Conor. > >> ..snip.. >> -- >> 2.25.1 >>
diff --git a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml index 153e146df7d4..efe0cacf55b7 100644 --- a/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml +++ b/Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml @@ -53,6 +53,12 @@ properties: - const: main - const: mm + power-domains: + maxItems: 1 + description: A phandle and PM domain specifier as defined by bindings of + the power controller specified by phandle. See + Documentation/devicetree/bindings/power/power-domain.yaml for details. + required: - compatible - reg @@ -67,6 +73,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h> #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt8173-power.h> pwm0: pwm@1401e000 { compatible = "mediatek,mt8173-disp-pwm"; @@ -75,4 +82,5 @@ examples: clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; clock-names = "main", "mm"; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; };
According to the Mediatek datasheet, the display PWM block has a power domain. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> --- Documentation/devicetree/bindings/pwm/mediatek,pwm-disp.yaml | 8 ++++++++ 1 file changed, 8 insertions(+)