Show patches with: Submitter = Samuel Holland       |    State = Action Required       |    Archived = No       |   57 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[v6,13/13] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,12/13] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,11/13] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,10/13] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-03-27 Samuel Holland New
[v6,06/13] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 2 - --- 2024-03-27 Samuel Holland New
[v6,05/13] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,04/13] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,03/13] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - 2 - --- 2024-03-27 Samuel Holland New
[v6,02/13] riscv: Factor out page table TLB synchronization riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v6,01/13] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-03-27 Samuel Holland New
[v5,13/13] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,12/13] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,11/13] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,10/13] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,09/13] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,08/13] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,07/13] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,06/13] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,05/13] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,04/13] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,03/13] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v5,02/13] riscv: Factor out page table TLB synchronization riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-02-29 Samuel Holland New
[v5,01/13] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-02-29 Samuel Holland New
[v4,12/12] riscv: mm: Always use an ASID to flush mm contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,11/12] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,10/12] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,09/12] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,08/12] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,07/12] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-01-02 Samuel Holland New
[v4,06/12] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-01-02 Samuel Holland New
[v4,05/12] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,04/12] riscv: Only send remote fences when some other CPU is online riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2024-01-02 Samuel Holland New
[v4,03/12] riscv: mm: Broadcast kernel TLB flushes only when needed riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,02/12] riscv: Use IPIs for remote cache/TLB flushes by default riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v4,01/12] riscv: Flush the instruction cache during SMP bringup riscv: ASID-related and UP-related TLB flush enhancements - 1 - --- 2024-01-02 Samuel Holland New
[v3,8/8] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,7/8] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,6/8] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,5/8] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,4/8] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,3/8] riscv: Avoid TLB flush loops when affected by SiFive CIP-1200 riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,2/8] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v3,1/8] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-11-22 Samuel Holland New
[v2,11/11] riscv: mm: Always use ASID to flush MM contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,10/11] riscv: mm: Preserve global TLB entries when switching contexts riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,09/11] riscv: mm: Make asid_bits a local variable riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,08/11] riscv: mm: Use a fixed layout for the MM context ID riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,07/11] riscv: mm: Introduce cntx2asid/cntx2version helper macros riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,06/11] riscv: Apply SiFive CIP-1200 workaround to single-ASID sfence.vma riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,05/11] riscv: mm: Combine the SMP and UP TLB flush code riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,04/11] riscv: Improve flush_tlb_kernel_range() riscv: ASID-related and UP-related TLB flush enhancements - 1 1 --- 2023-10-28 Samuel Holland New
[v2,03/11] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb riscv: ASID-related and UP-related TLB flush enhancements - 1 1 --- 2023-10-28 Samuel Holland New
[v2,02/11] riscv: Improve flush_tlb_range() for hugetlb pages riscv: ASID-related and UP-related TLB flush enhancements - - - --- 2023-10-28 Samuel Holland New
[v2,01/11] riscv: Improve tlb_flush() riscv: ASID-related and UP-related TLB flush enhancements - 1 1 --- 2023-10-28 Samuel Holland New