[RFC,18/48] RISC-V: KVM: Skip TLB management for TVMs

Message ID	20230419221716.3603068-19-atishp@rivosinc.com (mailing list archive)
State	New
Headers	show Return-Path: <owner-linux-mm@kvack.org> From: Atish Patra <atishp@rivosinc.com> To: linux-kernel@vger.kernel.org Cc: Atish Patra <atishp@rivosinc.com>, Alexandre Ghiti <alex@ghiti.fr>, Andrew Jones <ajones@ventanamicro.com>, Andrew Morton <akpm@linux-foundation.org>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>, Sean Christopherson <seanjc@google.com>, linux-coco@lists.linux.dev, Dylan Reid <dylan@rivosinc.com>, abrestic@rivosinc.com, Samuel Ortiz <sameo@rivosinc.com>, Christoph Hellwig <hch@infradead.org>, Conor Dooley <conor.dooley@microchip.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Guo Ren <guoren@kernel.org>, Heiko Stuebner <heiko@sntech.de>, Jiri Slaby <jirislaby@kernel.org>, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, Mayuresh Chitale <mchitale@ventanamicro.com>, Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>, Paul Walmsley <paul.walmsley@sifive.com>, Rajnesh Kanwal <rkanwal@rivosinc.com>, Uladzislau Rezki <urezki@gmail.com> Subject: [RFC 18/48] RISC-V: KVM: Skip TLB management for TVMs Date: Wed, 19 Apr 2023 15:16:46 -0700 Message-Id: <20230419221716.3603068-19-atishp@rivosinc.com> In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com> References: <20230419221716.3603068-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: owner-linux-mm@kvack.org Precedence: bulk
Series	RISC-V CoVE support \| expand [RFC,00/48] RISC-V CoVE support [RFC,01/48] mm/vmalloc: Introduce arch hooks to notify ioremap/unmap changes [RFC,02/48] RISC-V: KVM: Improve KVM error reporting to the user space [RFC,03/48] RISC-V: KVM: Invoke aia_update with preempt disabled/irq enabled [RFC,04/48] RISC-V: KVM: Add a helper function to get pgd size [RFC,05/48] RISC-V: Add COVH SBI extensions definitions [RFC,06/48] RISC-V: KVM: Implement COVH SBI extension [RFC,07/48] RISC-V: KVM: Add a barebone CoVE implementation [RFC,08/48] RISC-V: KVM: Add UABI to support static memory region attestation [RFC,09/48] RISC-V: KVM: Add CoVE related nacl helpers [RFC,10/48] RISC-V: KVM: Implement static memory region measurement [RFC,11/48] RISC-V: KVM: Use the new VM IOCTL for measuring pages [RFC,12/48] RISC-V: KVM: Exit to the user space for trap redirection [RFC,13/48] RISC-V: KVM: Return early for gstage modifications [RFC,14/48] RISC-V: KVM: Skip dirty logging updates for TVM [RFC,15/48] RISC-V: KVM: Add a helper function to trigger fence ops [RFC,16/48] RISC-V: KVM: Skip most VCPU requests for TVMs [RFC,17/48] RISC-V : KVM: Skip vmid/hgatp management for TVMs [RFC,18/48] RISC-V: KVM: Skip TLB management for TVMs [RFC,19/48] RISC-V: KVM: Register memory regions as confidential for TVMs [RFC,20/48] RISC-V: KVM: Add gstage mapping for TVMs [RFC,21/48] RISC-V: KVM: Handle SBI call forward from the TSM [RFC,22/48] RISC-V: KVM: Implement vcpu load/put functions for CoVE guests [RFC,23/48] RISC-V: KVM: Wireup TVM world switch [RFC,24/48] RISC-V: KVM: Update timer functionality for TVMs. [RFC,25/48] RISC-V: KVM: Skip HVIP update for TVMs [RFC,26/48] RISC-V: Add COVI extension definitions [RFC,27/48] RISC-V: KVM: Implement COVI SBI extension [RFC,28/48] RISC-V: KVM: Add interrupt management functions for TVM [RFC,29/48] RISC-V: KVM: Skip AIA CSR updates for TVMs [RFC,30/48] RISC-V: KVM: Perform limited operations in hardware enable/disable [RFC,31/48] RISC-V: KVM: Indicate no support user space emulated IRQCHIP [RFC,32/48] RISC-V: KVM: Add AIA support for TVMs [RFC,33/48] RISC-V: KVM: Hookup TVM VCPU init/destroy [RFC,34/48] RISC-V: KVM: Initialize CoVE [RFC,35/48] RISC-V: KVM: Add TVM init/destroy calls [RFC,36/48] RISC-V: KVM: Read/write gprs from/to shmem in case of TVM VCPU. [RFC,37/48] RISC-V: Add COVG SBI extension definitions [RFC,38/48] RISC-V: Add CoVE guest config and helper functions [RFC,39/48] RISC-V: Implement COVG SBI extension [RFC,40/48] RISC-V: COVE: Add COVH invalidate, validate, promote, demote and remove APIs. [RFC,41/48] RISC-V: KVM: Add host side support to handle COVG SBI calls. [RFC,42/48] RISC-V: Allow host to inject any ext interrupt id to a CoVE guest. [RFC,43/48] RISC-V: Add base memory encryption functions. [RFC,44/48] RISC-V: Add cc_platform_has() for RISC-V for CoVE [RFC,45/48] RISC-V: ioremap: Implement for arch specific ioremap hooks [RFC,46/48] riscv/virtio: Have CoVE guests enforce restricted virtio memory access. [RFC,47/48] RISC-V: Add shared bounce buffer to support DBCN for CoVE Guest. [RFC,48/48] drivers/hvc: sbi: Disable HVC console for TVMs

Message ID

20230419221716.3603068-19-atishp@rivosinc.com (mailing list archive)

State

New

Headers

From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Atish Patra <atishp@rivosinc.com>, Alexandre Ghiti <alex@ghiti.fr>,
 Andrew Jones <ajones@ventanamicro.com>,
 Andrew Morton <akpm@linux-foundation.org>, Anup Patel <anup@brainfault.org>,
 Atish Patra <atishp@atishpatra.org>,
 =?utf-8?b?QmrDtnJuIFTDtnBlbA==?= <bjorn@rivosinc.com>,
 Suzuki K Poulose <suzuki.poulose@arm.com>, Will Deacon <will@kernel.org>,
 Marc Zyngier <maz@kernel.org>, Sean Christopherson <seanjc@google.com>,
 linux-coco@lists.linux.dev, Dylan Reid <dylan@rivosinc.com>,
 abrestic@rivosinc.com, Samuel Ortiz <sameo@rivosinc.com>,
 Christoph Hellwig <hch@infradead.org>,
 Conor Dooley <conor.dooley@microchip.com>,
 Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Guo Ren <guoren@kernel.org>,
 Heiko Stuebner <heiko@sntech.de>, Jiri Slaby <jirislaby@kernel.org>,
 kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-mm@kvack.org,
 linux-riscv@lists.infradead.org,
 Mayuresh Chitale <mchitale@ventanamicro.com>,
 Palmer Dabbelt <palmer@dabbelt.com>, Paolo Bonzini <pbonzini@redhat.com>,
 Paul Walmsley <paul.walmsley@sifive.com>,
 Rajnesh Kanwal <rkanwal@rivosinc.com>, Uladzislau Rezki <urezki@gmail.com>
Subject: [RFC 18/48] RISC-V: KVM: Skip TLB management for TVMs
Date: Wed, 19 Apr 2023 15:16:46 -0700
Message-Id: <20230419221716.3603068-19-atishp@rivosinc.com>
In-Reply-To: <20230419221716.3603068-1-atishp@rivosinc.com>
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Series

RISC-V CoVE support | expand

Commit Message

Atish Patra April 19, 2023, 10:16 p.m. UTC

TSM manages the tlb entries for the TVMs. Thus, host can ignore
all the hfence requests or tlb updates for confidential guests.
Most of the hfence requests happen through vcpu requests which
are skipped for TVMs. Thus, we just need to take care of the
invocation from tlb management here.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
 arch/riscv/kvm/tlb.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kvm/tlb.c b/arch/riscv/kvm/tlb.c
index dff37b57..b007c02 100644
--- a/arch/riscv/kvm/tlb.c
+++ b/arch/riscv/kvm/tlb.c
@@ -15,6 +15,7 @@ 
 #include <asm/hwcap.h>
 #include <asm/insn-def.h>
 #include <asm/kvm_nacl.h>
+#include <asm/kvm_cove.h>
 
 #define has_svinval()	riscv_has_extension_unlikely(RISCV_ISA_EXT_SVINVAL)
 
@@ -72,6 +73,14 @@  void kvm_riscv_local_hfence_gvma_gpa(gpa_t gpa, gpa_t gpsz,
 
 void kvm_riscv_local_hfence_gvma_all(void)
 {
+	/* For TVMs, TSM will take care of hfence.
+	 * TODO: We can't skip unconditionally if cove is enabled
+	 * as the host may be running in HS-mode and need to issue hfence
+	 * for legacy VMs.
+	 */
+	if (kvm_riscv_cove_enabled())
+		return;
+
 	asm volatile(HFENCE_GVMA(zero, zero) : : : "memory");
 }
 
@@ -160,7 +169,7 @@  void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu)
 {
 	unsigned long vmid;
 
-	if (!kvm_riscv_gstage_vmid_bits() ||
+	if (is_cove_vcpu(vcpu) || !kvm_riscv_gstage_vmid_bits() ||
 	    vcpu->arch.last_exit_cpu == vcpu->cpu)
 		return;

[RFC,18/48] RISC-V: KVM: Skip TLB management for TVMs

Commit Message

Patch