| Message ID | 1649660143-22400-4-git-send-email-quic_rohiagar@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | SDX65 devicetree updates | expand |
On Mon, Apr 11, 2022 at 12:25:39PM +0530, Rohit Agarwal wrote: > Add devicetree support for SDHCI controller found in Qualcomm SDX65 > platform. The SDHCI controller is based on the MSM SDHCI v5 IP. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Thanks, Mani > --- > arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi > index 365df74..632ac78 100644 > --- a/arch/arm/boot/dts/qcom-sdx65.dtsi > +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi > @@ -168,6 +168,19 @@ > #interrupt-cells = <2>; > }; > > + sdhc_1: sdhci@8804000 { > + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0x08804000 0x1000>; > + reg-names = "hc_mem"; > + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", "pwr_irq"; > + clocks = <&gcc GCC_SDCC1_APPS_CLK>, > + <&gcc GCC_SDCC1_AHB_CLK>; > + clock-names = "core", "iface"; > + status = "disabled"; > + }; > + > pdc: interrupt-controller@b210000 { > compatible = "qcom,sdx65-pdc", "qcom,pdc"; > reg = <0xb210000 0x10000>; > -- > 2.7.4 >
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 365df74..632ac78 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -168,6 +168,19 @@ #interrupt-cells = <2>; }; + sdhc_1: sdhci@8804000 { + compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc_mem"; + interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + pdc: interrupt-controller@b210000 { compatible = "qcom,sdx65-pdc", "qcom,pdc"; reg = <0xb210000 0x10000>;
Add devicetree support for SDHCI controller found in Qualcomm SDX65 platform. The SDHCI controller is based on the MSM SDHCI v5 IP. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> --- arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)