| Message ID | 20240102-j7200-pcie-s2r-v4-18-6f1f53390c85@bootlin.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add suspend to ram support for PCIe on J7200 | expand |
On Mon, Mar 04, 2024 at 04:36:01PM +0100, Thomas Richard wrote: > From: Théo Lebrun <theo.lebrun@bootlin.com> > > Add suspend and resume support. Only the rc mode is supported. > > During the suspend stage PERST# is asserted, then deasserted during the > resume stage. > > Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> > Signed-off-by: Thomas Richard <thomas.richard@bootlin.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Regards, Siddharth. > --- > drivers/pci/controller/cadence/pci-j721e.c | 86 ++++++++++++++++++++++++++++++ > 1 file changed, 86 insertions(+) > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > index 9af4fd64c1f9..a1f1232e8ee5 100644 > --- a/drivers/pci/controller/cadence/pci-j721e.c > +++ b/drivers/pci/controller/cadence/pci-j721e.c > @@ -7,6 +7,8 @@ > */ > > #include <linux/clk.h> > +#include <linux/clk-provider.h> > +#include <linux/container_of.h> > #include <linux/delay.h> > #include <linux/gpio/consumer.h> > #include <linux/io.h> > @@ -22,6 +24,8 @@ > #include "../../pci.h" > #include "pcie-cadence.h" > > +#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) > + > #define ENABLE_REG_SYS_2 0x108 > #define STATUS_REG_SYS_2 0x508 > #define STATUS_CLR_REG_SYS_2 0x708 > @@ -588,6 +592,87 @@ static void j721e_pcie_remove(struct platform_device *pdev) > pm_runtime_disable(dev); > } > > +static int j721e_pcie_suspend_noirq(struct device *dev) > +{ > + struct j721e_pcie *pcie = dev_get_drvdata(dev); > + > + if (pcie->mode == PCI_MODE_RC) { > + gpiod_set_value_cansleep(pcie->reset_gpio, 0); > + clk_disable_unprepare(pcie->refclk); > + } > + > + cdns_pcie_disable_phy(pcie->cdns_pcie); > + > + return 0; > +} > + > +static int j721e_pcie_resume_noirq(struct device *dev) > +{ > + struct j721e_pcie *pcie = dev_get_drvdata(dev); > + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; > + int ret; > + > + ret = j721e_pcie_ctrl_init(pcie); > + if (ret < 0) > + return ret; > + > + j721e_pcie_config_link_irq(pcie); > + > + /* > + * This is not called explicitly in the probe, it is called by > + * cdns_pcie_init_phy(). > + */ > + ret = cdns_pcie_enable_phy(pcie->cdns_pcie); > + if (ret < 0) > + return ret; > + > + if (pcie->mode == PCI_MODE_RC) { > + struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie); > + > + ret = clk_prepare_enable(pcie->refclk); > + if (ret < 0) > + return ret; > + > + /* > + * "Power Sequencing and Reset Signal Timings" table in > + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 > + * indicates PERST# should be deasserted after minimum of 100us > + * once REFCLK is stable. The REFCLK to the connector in RC > + * mode is selected while enabling the PHY. So deassert PERST# > + * after 100 us. > + */ > + if (pcie->reset_gpio) { > + fsleep(100); > + gpiod_set_value_cansleep(pcie->reset_gpio, 1); > + } > + > + ret = cdns_pcie_host_link_setup(rc); > + if (ret < 0) { > + clk_disable_unprepare(pcie->refclk); > + return ret; > + } > + > + /* > + * Reset internal status of BARs to force reinitialization in > + * cdns_pcie_host_init(). > + */ > + for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++) > + rc->avail_ib_bar[bar] = true; > + > + ret = cdns_pcie_host_init(rc); > + if (ret) { > + clk_disable_unprepare(pcie->refclk); > + return ret; > + } > + } > + > + return 0; > +} > + > +static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops, > + j721e_pcie_suspend_noirq, > + j721e_pcie_resume_noirq); > + > static struct platform_driver j721e_pcie_driver = { > .probe = j721e_pcie_probe, > .remove_new = j721e_pcie_remove, > @@ -595,6 +680,7 @@ static struct platform_driver j721e_pcie_driver = { > .name = "j721e-pcie", > .of_match_table = of_j721e_pcie_match, > .suppress_bind_attrs = true, > + .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), > }, > }; > builtin_platform_driver(j721e_pcie_driver); > > -- > 2.39.2 > >
On Mon, Mar 04, 2024 at 04:36:01PM +0100, Thomas Richard wrote: > From: Théo Lebrun <theo.lebrun@bootlin.com> > > Add suspend and resume support. Only the rc mode is supported. > > During the suspend stage PERST# is asserted, then deasserted during the > resume stage. > + * "Power Sequencing and Reset Signal Timings" table in > + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 > + * indicates PERST# should be deasserted after minimum of 100us > + * once REFCLK is stable. The REFCLK to the connector in RC > + * mode is selected while enabling the PHY. So deassert PERST# > + * after 100 us. Please cite current spec (r5.1 was published August 2023), section, and parameter name. I think this is T_PERST-CLK, "REFCLK stable before PERST# inactive", from sec 2.9.2. > + */ > + if (pcie->reset_gpio) { > + fsleep(100); I'd like to see a macro used here instead of a bare number. Since this isn't anything specific to j721e, maybe add something like #define PCIE_T_PERST_CLK_US alongside PCIE_T_PVPERL_MS. > + gpiod_set_value_cansleep(pcie->reset_gpio, 1); > + }
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 9af4fd64c1f9..a1f1232e8ee5 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -7,6 +7,8 @@ */ #include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/container_of.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/io.h> @@ -22,6 +24,8 @@ #include "../../pci.h" #include "pcie-cadence.h" +#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie) + #define ENABLE_REG_SYS_2 0x108 #define STATUS_REG_SYS_2 0x508 #define STATUS_CLR_REG_SYS_2 0x708 @@ -588,6 +592,87 @@ static void j721e_pcie_remove(struct platform_device *pdev) pm_runtime_disable(dev); } +static int j721e_pcie_suspend_noirq(struct device *dev) +{ + struct j721e_pcie *pcie = dev_get_drvdata(dev); + + if (pcie->mode == PCI_MODE_RC) { + gpiod_set_value_cansleep(pcie->reset_gpio, 0); + clk_disable_unprepare(pcie->refclk); + } + + cdns_pcie_disable_phy(pcie->cdns_pcie); + + return 0; +} + +static int j721e_pcie_resume_noirq(struct device *dev) +{ + struct j721e_pcie *pcie = dev_get_drvdata(dev); + struct cdns_pcie *cdns_pcie = pcie->cdns_pcie; + int ret; + + ret = j721e_pcie_ctrl_init(pcie); + if (ret < 0) + return ret; + + j721e_pcie_config_link_irq(pcie); + + /* + * This is not called explicitly in the probe, it is called by + * cdns_pcie_init_phy(). + */ + ret = cdns_pcie_enable_phy(pcie->cdns_pcie); + if (ret < 0) + return ret; + + if (pcie->mode == PCI_MODE_RC) { + struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie); + + ret = clk_prepare_enable(pcie->refclk); + if (ret < 0) + return ret; + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 3.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (pcie->reset_gpio) { + fsleep(100); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); + } + + ret = cdns_pcie_host_link_setup(rc); + if (ret < 0) { + clk_disable_unprepare(pcie->refclk); + return ret; + } + + /* + * Reset internal status of BARs to force reinitialization in + * cdns_pcie_host_init(). + */ + for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++) + rc->avail_ib_bar[bar] = true; + + ret = cdns_pcie_host_init(rc); + if (ret) { + clk_disable_unprepare(pcie->refclk); + return ret; + } + } + + return 0; +} + +static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops, + j721e_pcie_suspend_noirq, + j721e_pcie_resume_noirq); + static struct platform_driver j721e_pcie_driver = { .probe = j721e_pcie_probe, .remove_new = j721e_pcie_remove, @@ -595,6 +680,7 @@ static struct platform_driver j721e_pcie_driver = { .name = "j721e-pcie", .of_match_table = of_j721e_pcie_match, .suppress_bind_attrs = true, + .pm = pm_sleep_ptr(&j721e_pcie_pm_ops), }, }; builtin_platform_driver(j721e_pcie_driver);