[v2,0/2] Add Stratix10 PCIe Root Port support

Message

Tan, Ley Foon Dec. 31, 2018, 8:24 a.m. UTC

Add PCIe Root Port support for Stratix10 device and also update
device tree binding documentation.

v1 -> v2:
---------
- Add define S10_TLP_FMTTYPE_* macros.
- Remove initialize structure members to NULL/zero.
- Rename *_funcs to *_data.
- Update comment and fix coding style warning from checkpatch.pl.
- Rename StratixXX to stratix10.

History:
--------
[v1]: https://lkml.org/lkml/2018/12/26/68

Ley Foon Tan (2):
  pci: altera: Add Stratix10 PCIe support
  Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0

 .../devicetree/bindings/pci/altera-pcie.txt        |    4 +-
 drivers/pci/controller/Kconfig                     |    2 +-
 drivers/pci/controller/pcie-altera.c               |  240 ++++++++++++++++++--
 3 files changed, 220 insertions(+), 26 deletions(-)

Comments

Bjorn Helgaas Dec. 31, 2018, 4:15 p.m. UTC | #1

On Mon, Dec 31, 2018 at 04:24:51PM +0800, Ley Foon Tan wrote:
> Add PCIe Root Port support for Stratix10 device and also update

"Stratix10" is a big step better than "StratixXX" because a web search
for the latter finds nothing, while the former does find useful
things.

Intel materials on the web seem to use "Stratix 10".  You might as
well include the space in English text.

Tan, Ley Foon Jan. 2, 2019, 1:31 a.m. UTC | #2

On Mon, 2018-12-31 at 10:15 -0600, Bjorn Helgaas wrote:
> On Mon, Dec 31, 2018 at 04:24:51PM +0800, Ley Foon Tan wrote:
> > 
> > Add PCIe Root Port support for Stratix10 device and also update
> "Stratix10" is a big step better than "StratixXX" because a web
> search
> for the latter finds nothing, while the former does find useful
> things.
> 
> Intel materials on the web seem to use "Stratix 10".  You might as
> well include the space in English text.
Okay, will change to Stratix 10.

Regards
Ley Foon