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[v7,0/2] Adding support for Versal CPM as Root Port driver

Message ID 1588852716-23132-1-git-send-email-bharat.kumar.gogada@xilinx.com (mailing list archive)
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Series Adding support for Versal CPM as Root Port driver | expand

Message

Bharat Kumar Gogada May 7, 2020, 11:58 a.m. UTC 
- Adding support for Versal CPM as Root port.
- The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrated
  block for CPM along with the integrated bridge can function
  as PCIe Root Port.
- Versal CPM uses GICv3 ITS feature for assigning MSI/MSI-X
  vectors and handling MSI/MSI-X interrupts.
- Bridge error and legacy interrupts in Versal CPM are handled using
  Versal CPM specific interrupt line.

Changes for v7:
- Adding device tree documentation as schema.
- Using pci_host_probe for registering bridge.

Bharat Kumar Gogada (2):
  PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port
  PCI: xilinx-cpm: Add Versal CPM Root Port driver

 .../devicetree/bindings/pci/xilinx-versal-cpm.yaml | 105 +++++
 drivers/pci/controller/Kconfig                     |   9 +
 drivers/pci/controller/Makefile                    |   1 +
 drivers/pci/controller/pcie-xilinx-cpm.c           | 506 +++++++++++++++++++++
 4 files changed, 621 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
 create mode 100644 drivers/pci/controller/pcie-xilinx-cpm.c