| Message ID | 20210921220459.2437386-1-ben.widawsky@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | cxl_pci refactor for reusability | expand |
On 21-09-21 15:04:52, Ben Widawsky wrote: > Provide the ability to obtain CXL register blocks as discrete functionality. > This functionality will become useful for other CXL drivers that need access to > CXL register blocks. It is also in line with other additions to core which moves > register mapping functionality. > > At the introduction of the CXL driver the only user of CXL MMIO was cxl_pci > (then known as cxl_mem). As the driver has evolved it is clear that cxl_pci will > not be the only entity that needs access to CXL MMIO. This series stops short of > moving the generalized functionality into cxl_core for the sake of getting eyes > on the important foundational bits sooner rather than later. The ultimate plan > is to move much of the code into cxl_core. > > Via review of two previous patches [1] & [2] it has been suggested that the bits > which are being used for DVSEC enumeration move into PCI core. As CXL core is > soon going to require these, let's try to get the ball rolling now on making > that happen. > > [1]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/ Dangit. https://lore.kernel.org/linux-pci/20210913190131.xiiszmno46qie7v5@intel.com/ > [2]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/ > > Ben Widawsky (7): > cxl: Convert "RBI" to enum > cxl/pci: Remove dev_dbg for unknown register blocks > cxl/pci: Refactor cxl_pci_setup_regs > cxl/pci: Make more use of cxl_register_map > PCI: Add pci_find_dvsec_capability to find designated VSEC > cxl/pci: Use pci core's DVSEC functionality > ocxl: Use pci core's DVSEC functionality > > drivers/cxl/pci.c | 144 ++++++++++++++++++------------------- > drivers/cxl/pci.h | 14 ++-- > drivers/misc/ocxl/config.c | 13 +--- > drivers/pci/pci.c | 32 +++++++++ > include/linux/pci.h | 1 + > 5 files changed, 113 insertions(+), 91 deletions(-) > > -- > 2.33.0 >
On Tue, Sep 21, 2021 at 3:05 PM Ben Widawsky <ben.widawsky@intel.com> wrote: > > Provide the ability to obtain CXL register blocks as discrete functionality. > This functionality will become useful for other CXL drivers that need access to > CXL register blocks. It is also in line with other additions to core which moves > register mapping functionality. > > At the introduction of the CXL driver the only user of CXL MMIO was cxl_pci > (then known as cxl_mem). As the driver has evolved it is clear that cxl_pci will > not be the only entity that needs access to CXL MMIO. This series stops short of > moving the generalized functionality into cxl_core for the sake of getting eyes > on the important foundational bits sooner rather than later. The ultimate plan > is to move much of the code into cxl_core. > > Via review of two previous patches [1] & [2] it has been suggested that the bits > which are being used for DVSEC enumeration move into PCI core. As CXL core is > soon going to require these, let's try to get the ball rolling now on making > that happen. > > [1]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/ > [2]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/ > > Ben Widawsky (7): > cxl: Convert "RBI" to enum > cxl/pci: Remove dev_dbg for unknown register blocks > cxl/pci: Refactor cxl_pci_setup_regs > cxl/pci: Make more use of cxl_register_map > PCI: Add pci_find_dvsec_capability to find designated VSEC > cxl/pci: Use pci core's DVSEC functionality > ocxl: Use pci core's DVSEC functionality I also found: siov_find_pci_dvsec() ...and an open coded one in: drivers/mfd/intel_pmt.c::pmt_pci_probe() This one looks too weird to replace: arch/x86/events/intel/uncore_discovery.c::intel_uncore_has_discovery_tables() In any event I'd expect this cover to also be cc'd to those folks.
On 21-09-21 15:28:21, Dan Williams wrote: > On Tue, Sep 21, 2021 at 3:05 PM Ben Widawsky <ben.widawsky@intel.com> wrote: > > > > Provide the ability to obtain CXL register blocks as discrete functionality. > > This functionality will become useful for other CXL drivers that need access to > > CXL register blocks. It is also in line with other additions to core which moves > > register mapping functionality. > > > > At the introduction of the CXL driver the only user of CXL MMIO was cxl_pci > > (then known as cxl_mem). As the driver has evolved it is clear that cxl_pci will > > not be the only entity that needs access to CXL MMIO. This series stops short of > > moving the generalized functionality into cxl_core for the sake of getting eyes > > on the important foundational bits sooner rather than later. The ultimate plan > > is to move much of the code into cxl_core. > > > > Via review of two previous patches [1] & [2] it has been suggested that the bits > > which are being used for DVSEC enumeration move into PCI core. As CXL core is > > soon going to require these, let's try to get the ball rolling now on making > > that happen. > > > > [1]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/ > > [2]: https://lore.kernel.org/linux-cxl/20210920225638.1729482-1-ben.widawsky@intel.com/ > > > > Ben Widawsky (7): > > cxl: Convert "RBI" to enum > > cxl/pci: Remove dev_dbg for unknown register blocks > > cxl/pci: Refactor cxl_pci_setup_regs > > cxl/pci: Make more use of cxl_register_map > > PCI: Add pci_find_dvsec_capability to find designated VSEC > > cxl/pci: Use pci core's DVSEC functionality > > ocxl: Use pci core's DVSEC functionality > > I also found: > > siov_find_pci_dvsec() Hadn't seen this one... Thanks. > > ...and an open coded one in: > > drivers/mfd/intel_pmt.c::pmt_pci_probe() I had spotted this one previously > > This one looks too weird to replace: > > arch/x86/events/intel/uncore_discovery.c::intel_uncore_has_discovery_tables() > > In any event I'd expect this cover to also be cc'd to those folks. I did Cc OCXL in the relevant patch, I don't think they need most of the background in the cover letter (I also did Cc David Box who maintains intel_pmt). I'll add them to the cover letter here shortly...