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[0/2] Add support for Xilinx Versal CPM5 Root Port

Message ID 20220207041250.1658-1-bharat.kumar.gogada@xilinx.com (mailing list archive)
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Series Add support for Xilinx Versal CPM5 Root Port | expand

Message

Bharat Kumar Gogada Feb. 7, 2022, 4:12 a.m. UTC 
Xilinx Versal Premium series has CPM5 block which supports Root port
functioning at Gen5 speed.
Xilinx Versal CPM5 has few changes with existing CPM block.
- CPM5 has dedicated register space for control and status registers.
- CPM5 legacy interrupt handling needs additonal register bit
  to enable and handle legacy interrupts.

Bharat Kumar Gogada (2):
  PCI: xilinx-cpm: Update YAML schemas for Versal CPM5 Root Port
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port driver

 .../bindings/pci/xilinx-versal-cpm.yaml       | 47 ++++++++++++++++---
 drivers/pci/controller/pcie-xilinx-cpm.c      | 33 ++++++++++++-
 2 files changed, 72 insertions(+), 8 deletions(-)