| Message ID | 20220215124606.28627-1-bharat.kumar.gogada@xilinx.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for Xilinx Versal CPM5 Root Port | expand |
Ping > -----Original Message----- > From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> > Sent: Tuesday, February 15, 2022 6:16 PM > To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: lorenzo.pieralisi@arm.com; bhelgaas@google.com; Michal Simek > <michals@xilinx.com>; Bharat Kumar Gogada <bharatku@xilinx.com> > Subject: [PATCH v2 0/2] Add support for Xilinx Versal CPM5 Root Port > > Xilinx Versal Premium series has CPM5 block which supports Root Port > functioning at Gen5 speed. > > Xilinx Versal CPM5 has few changes with existing CPM block. > - CPM5 has dedicated register space for control and status registers. > - CPM5 legacy interrupt handling needs additonal register bit > to enable and handle legacy interrupts. > > Changes in v2: > - changed commit message. > > Bharat Kumar Gogada (2): > dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port > PCI: xilinx-cpm: Add support for Versal CPM5 Root Port > > .../bindings/pci/xilinx-versal-cpm.yaml | 47 ++++++++++++++++--- > drivers/pci/controller/pcie-xilinx-cpm.c | 33 ++++++++++++- > 2 files changed, 72 insertions(+), 8 deletions(-) > > -- > 2.17.1