| Message ID | 20220512172909.2436302-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: qcom: Rework pipe_clk/pipe_clk_src handling | expand |
On Thu, May 12, 2022 at 08:29:04PM +0300, Dmitry Baryshkov wrote: > PCIe pipe clk (and some other clocks) must be parked to the "safe" > source (bi_tcxo) when corresponding GDSC is turned off and on again. > Currently this is handcoded in the PCIe driver by reparenting the > gcc_pipe_N_clk_src clock. > > Instead of doing it manually, follow the approach used by > clk_rcg2_shared_ops and implement this parking in the enable() and > disable() clock operations for respective pipe clocks. > > PCIe part depends on [1]. This one was merged a month ago. > Changes since v4: > - Renamed the clock to clk-regmap-pipe-src, > - Added mention of PCIe2 PHY to the commit message, > - Expanded commit messages to mention additional pipe clock details. > > Changes since v3: > - Replaced the clock multiplexer implementation with branch-like clock. > > Changes since v2: > - Added is_enabled() callback > - Added default parent to the pipe clock configuration > > Changes since v1: > - Rebased on top of [1]. > - Removed erroneous Fixes tag from the patch 4. > > Changes since RFC: > - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather > than specifying the register value directly > - Expand commit message to the first patch to specially mention that > it is required only on newer generations of Qualcomm chipsets. > > [1]: https://lore.kernel.org/all/20220401133351.10113-1-johan+linaro@kernel.org/ Johan
On Fri, 13 May 2022 at 10:41, Johan Hovold <johan@kernel.org> wrote: > > On Thu, May 12, 2022 at 08:29:04PM +0300, Dmitry Baryshkov wrote: > > PCIe pipe clk (and some other clocks) must be parked to the "safe" > > source (bi_tcxo) when corresponding GDSC is turned off and on again. > > Currently this is handcoded in the PCIe driver by reparenting the > > gcc_pipe_N_clk_src clock. > > > > Instead of doing it manually, follow the approach used by > > clk_rcg2_shared_ops and implement this parking in the enable() and > > disable() clock operations for respective pipe clocks. > > > > PCIe part depends on [1]. > > This one was merged a month ago. It is not in Linus's tree (only in Lorenzo's one). So anybody wishing to test the series would still have to pick it up manually. > > > Changes since v4: > > - Renamed the clock to clk-regmap-pipe-src, > > - Added mention of PCIe2 PHY to the commit message, > > - Expanded commit messages to mention additional pipe clock details. > > > > Changes since v3: > > - Replaced the clock multiplexer implementation with branch-like clock. > > > > Changes since v2: > > - Added is_enabled() callback > > - Added default parent to the pipe clock configuration > > > > Changes since v1: > > - Rebased on top of [1]. > > - Removed erroneous Fixes tag from the patch 4. > > > > Changes since RFC: > > - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather > > than specifying the register value directly > > - Expand commit message to the first patch to specially mention that > > it is required only on newer generations of Qualcomm chipsets. > > > > [1]: https://lore.kernel.org/all/20220401133351.10113-1-johan+linaro@kernel.org/ > > Johan
On Fri, May 13, 2022 at 12:31:27PM +0300, Dmitry Baryshkov wrote: > On Fri, 13 May 2022 at 10:41, Johan Hovold <johan@kernel.org> wrote: > > On Thu, May 12, 2022 at 08:29:04PM +0300, Dmitry Baryshkov wrote: > > > PCIe part depends on [1]. > > > > This one was merged a month ago. > > It is not in Linus's tree (only in Lorenzo's one). So anybody wishing > to test the series would still have to pick it up manually. Fair enough, but you generally don't need to describe dependencies that have already been picked up by the maintainer. Johan
PCIe pipe clk (and some other clocks) must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. Instead of doing it manually, follow the approach used by clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations for respective pipe clocks. PCIe part depends on [1]. Changes since v4: - Renamed the clock to clk-regmap-pipe-src, - Added mention of PCIe2 PHY to the commit message, - Expanded commit messages to mention additional pipe clock details. Changes since v3: - Replaced the clock multiplexer implementation with branch-like clock. Changes since v2: - Added is_enabled() callback - Added default parent to the pipe clock configuration Changes since v1: - Rebased on top of [1]. - Removed erroneous Fixes tag from the patch 4. Changes since RFC: - Rework clk-regmap-mux fields. Specify safe parent as P_* value rather than specifying the register value directly - Expand commit message to the first patch to specially mention that it is required only on newer generations of Qualcomm chipsets. [1]: https://lore.kernel.org/all/20220401133351.10113-1-johan+linaro@kernel.org/ Dmitry Baryshkov (5): PCI: qcom: Remove unnecessary pipe_clk handling clk: qcom: regmap: add PHY clock source implementation clk: qcom: gcc-sm8450: use new clk_regmap_pipe_src_ops for PCIe pipe clocks clk: qcom: gcc-sc7280: use new clk_regmap_pipe_src_ops for PCIe pipe clocks PCI: qcom: Drop manual pipe_clk_src handling drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-regmap-pipe-src.c | 62 ++++++++++++++++++++ drivers/clk/qcom/clk-regmap-pipe-src.h | 24 ++++++++ drivers/clk/qcom/gcc-sc7280.c | 49 ++++++---------- drivers/clk/qcom/gcc-sm8450.c | 51 ++++++---------- drivers/pci/controller/dwc/pcie-qcom.c | 81 +------------------------- 6 files changed, 128 insertions(+), 140 deletions(-) create mode 100644 drivers/clk/qcom/clk-regmap-pipe-src.c create mode 100644 drivers/clk/qcom/clk-regmap-pipe-src.h base-commit: 3123109284176b1532874591f7c81f3837bbdc17 prerequisite-patch-id: 71e4b5b7ff5d87f2407735cc6a3074812cde3697