| Message ID | 20220523181836.2019180-1-dmitry.baryshkov@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | PCI: qcom: Fix higher MSI vectors handling | expand |
On Mon, May 23, 2022 at 09:18:28PM +0300, Dmitry Baryshkov wrote: > I have replied with my Tested-by to the patch at [2], which has landed > in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: > Add support for handling MSIs from 8 endpoints"). However lately I > noticed that during the tests I still had 'pcie_pme=nomsi', so the > device was not forced to use higher MSI vectors. > > After removing this option I noticed that hight MSI vectors are not > delivered on tested platforms. After additional research I stumbled upon > a patch in msm-4.14 ([1]), which describes that each group of MSI > vectors is mapped to the separate interrupt. Implement corresponding > mapping. > > The first patch in the series is a revert of [2] (landed in pci-next). > Either both patches should be applied or both should be dropped. 20f1bfb8dd62 is currently on Lorenzo's pci/qcom branch: $ git log --oneline remotes/lorenzo/pci/qcom bddedfeb1315 dt-bindings: PCI: qcom: Add schema for sc7280 chipset a6f2d6b1b349 dt-bindings: PCI: qcom: Specify reg-names explicitly 81dab110d351 dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms 5383d16f0607 dt-bindings: PCI: qcom: Convert to YAML 3ae93c5a9718 PCI: qcom: Fix unbalanced PHY init on probe errors b986db29edbb PCI: qcom: Fix runtime PM imbalance on probe errors dcd9011f591a PCI: qcom: Fix pipe clock imbalance 3007ba831ccd PCI: qcom: Add SM8150 SoC support f52d2a0f0d32 dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC 20f1bfb8dd62 PCI: qcom: Add support for handling MSIs from 8 endpoints 312310928417 Linux 5.18-rc1 Is it safe for me to just drop that single patch before sending the pull request for v5.19? Then target the rest of this series for v5.20? Bjorn
On Tue, 24 May 2022 at 17:53, Bjorn Helgaas <helgaas@kernel.org> wrote: > > On Mon, May 23, 2022 at 09:18:28PM +0300, Dmitry Baryshkov wrote: > > I have replied with my Tested-by to the patch at [2], which has landed > > in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: > > Add support for handling MSIs from 8 endpoints"). However lately I > > noticed that during the tests I still had 'pcie_pme=nomsi', so the > > device was not forced to use higher MSI vectors. > > > > After removing this option I noticed that hight MSI vectors are not > > delivered on tested platforms. After additional research I stumbled upon > > a patch in msm-4.14 ([1]), which describes that each group of MSI > > vectors is mapped to the separate interrupt. Implement corresponding > > mapping. > > > > The first patch in the series is a revert of [2] (landed in pci-next). > > Either both patches should be applied or both should be dropped. > > 20f1bfb8dd62 is currently on Lorenzo's pci/qcom branch: > > $ git log --oneline remotes/lorenzo/pci/qcom > bddedfeb1315 dt-bindings: PCI: qcom: Add schema for sc7280 chipset > a6f2d6b1b349 dt-bindings: PCI: qcom: Specify reg-names explicitly > 81dab110d351 dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms > 5383d16f0607 dt-bindings: PCI: qcom: Convert to YAML > 3ae93c5a9718 PCI: qcom: Fix unbalanced PHY init on probe errors > b986db29edbb PCI: qcom: Fix runtime PM imbalance on probe errors > dcd9011f591a PCI: qcom: Fix pipe clock imbalance > 3007ba831ccd PCI: qcom: Add SM8150 SoC support > f52d2a0f0d32 dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC > 20f1bfb8dd62 PCI: qcom: Add support for handling MSIs from 8 endpoints > 312310928417 Linux 5.18-rc1 > > Is it safe for me to just drop that single patch before sending the > pull request for v5.19? Then target the rest of this series for > v5.20? Yes and yes.
On Tue, May 24, 2022 at 07:17:42PM +0300, Dmitry Baryshkov wrote: > On Tue, 24 May 2022 at 17:53, Bjorn Helgaas <helgaas@kernel.org> wrote: > > > > On Mon, May 23, 2022 at 09:18:28PM +0300, Dmitry Baryshkov wrote: > > > I have replied with my Tested-by to the patch at [2], which has landed > > > in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: > > > Add support for handling MSIs from 8 endpoints"). However lately I > > > noticed that during the tests I still had 'pcie_pme=nomsi', so the > > > device was not forced to use higher MSI vectors. > > > > > > After removing this option I noticed that hight MSI vectors are not > > > delivered on tested platforms. After additional research I stumbled upon > > > a patch in msm-4.14 ([1]), which describes that each group of MSI > > > vectors is mapped to the separate interrupt. Implement corresponding > > > mapping. > > > > > > The first patch in the series is a revert of [2] (landed in pci-next). > > > Either both patches should be applied or both should be dropped. > > > > 20f1bfb8dd62 is currently on Lorenzo's pci/qcom branch: > > > > $ git log --oneline remotes/lorenzo/pci/qcom > > bddedfeb1315 dt-bindings: PCI: qcom: Add schema for sc7280 chipset > > a6f2d6b1b349 dt-bindings: PCI: qcom: Specify reg-names explicitly > > 81dab110d351 dt-bindings: PCI: qcom: Do not require resets on msm8996 platforms > > 5383d16f0607 dt-bindings: PCI: qcom: Convert to YAML > > 3ae93c5a9718 PCI: qcom: Fix unbalanced PHY init on probe errors > > b986db29edbb PCI: qcom: Fix runtime PM imbalance on probe errors > > dcd9011f591a PCI: qcom: Fix pipe clock imbalance > > 3007ba831ccd PCI: qcom: Add SM8150 SoC support > > f52d2a0f0d32 dt-bindings: pci: qcom: Document PCIe bindings for SM8150 SoC > > 20f1bfb8dd62 PCI: qcom: Add support for handling MSIs from 8 endpoints > > 312310928417 Linux 5.18-rc1 > > > > Is it safe for me to just drop that single patch before sending the > > pull request for v5.19? Then target the rest of this series for > > v5.20? > > Yes and yes. Great, thank you! I have dropped that one from my "next" branch.
On Mon, May 23, 2022 at 09:18:28PM +0300, Dmitry Baryshkov wrote: > I have replied with my Tested-by to the patch at [2], which has landed > in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: > Add support for handling MSIs from 8 endpoints"). However lately I > noticed that during the tests I still had 'pcie_pme=nomsi', so the > device was not forced to use higher MSI vectors. > > After removing this option I noticed that hight MSI vectors are not > delivered on tested platforms. After additional research I stumbled upon > a patch in msm-4.14 ([1]), which describes that each group of MSI > vectors is mapped to the separate interrupt. Implement corresponding > mapping. > > The first patch in the series is a revert of [2] (landed in pci-next). > Either both patches should be applied or both should be dropped. > > Patchseries dependecies: [3] (for the schema change). > > Changes since v11 (suggested by Johan): > - Added back reporting errors for the "msi0" interrupt, > - Stopped overriding num_vectors field if it is less than the amount of > MSI vectors deduced from interrupt list, > - Added a warning (and an override) if the host specifies more MSI > vectors than available, > - Moved has_split_msi_irq variable to the patch where it is used. You forgot to CC me this version. Please remember to keep reviewers on CC. Johan
I have replied with my Tested-by to the patch at [2], which has landed in the linux-next as the commit 20f1bfb8dd62 ("PCI: qcom: Add support for handling MSIs from 8 endpoints"). However lately I noticed that during the tests I still had 'pcie_pme=nomsi', so the device was not forced to use higher MSI vectors. After removing this option I noticed that hight MSI vectors are not delivered on tested platforms. After additional research I stumbled upon a patch in msm-4.14 ([1]), which describes that each group of MSI vectors is mapped to the separate interrupt. Implement corresponding mapping. The first patch in the series is a revert of [2] (landed in pci-next). Either both patches should be applied or both should be dropped. Patchseries dependecies: [3] (for the schema change). Changes since v11 (suggested by Johan): - Added back reporting errors for the "msi0" interrupt, - Stopped overriding num_vectors field if it is less than the amount of MSI vectors deduced from interrupt list, - Added a warning (and an override) if the host specifies more MSI vectors than available, - Moved has_split_msi_irq variable to the patch where it is used. Changes since v10: - Remove has_split_msi_irqs flag. Trust DT and use split MSI IRQs if they are described in the DT. This removes the need for the pcie-qcom.c changes (everything is handled by the core (suggested by Johan). - Rebased on top of Lorenzo's DWC branch Changes since v9: - Relax requirements and stop validating the DT. If the has_split_msi was specified, parse as many msiN irqs as specified in DT. If there are none, fallback to the single "msi" IRQ. Changes since v8: - Fix typos noted by Bjorn Helgaas - Add missing links to the patch 1 (revert) - Fix sm8250 interrupt-names (Johan) - Specify num_vectors in qcom configuration data (Johan) - Rework parsing of MSI IRQs (Johan) Changes since v7: - Move code back to the dwc core driver (as required by Rob), - Change dt schema to require either a single "msi" interrupt or an array of "msi0", "msi1", ... "msi7" IRQs. Disallow specifying a part of the array (the DT should specify the exact amount of MSI IRQs allowing fallback to a single "msi" IRQ), - Fix in the DWC init code for the dma_mapping_error() return value. Changes since v6: - Fix indentation of the arguments as requested by Stanimir Changes since v5: - Fixed commit subject and in-comment code according to Bjorn's suggestion, - Changed variable idx to i to follow dw_handle_msi_irq() style. Changes since v4: - Fix the minItems/maxItems properties in the YAML schema. Changes since v3: - Reimplement MSI handling scheme in the Qualcomm host controller driver. Changes since v2: - Fix and rephrase commit message for patch 2. Changes since v1: - Split a huge patch into three patches as suggested by Bjorn Helgaas - snps,dw-pcie removal is now part of [3] [1] https://git.codelinaro.org/clo/la/kernel/msm-4.14/-/commit/671a3d5f129f4bfe477152292ada2194c8440d22 [2] https://lore.kernel.org/linux-arm-msm/20211214101319.25258-1-manivannan.sadhasivam@linaro.org/ [3] https://lore.kernel.org/linux-arm-msm/20220422211002.2012070-1-dmitry.baryshkov@linaro.org/ Dmitry Baryshkov (8): PCI: qcom: Revert "PCI: qcom: Add support for handling MSIs from 8 endpoints" PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi() PCI: dwc: Convert msi_irq to the array PCI: dwc: split MSI IRQ parsing/allocation to a separate function PCI: dwc: Handle MSIs routed to multiple GIC interrupts PCI: dwc: Implement special ISR handler for split MSI IRQ setup dt-bindings: PCI: qcom: Support additional MSI interrupts arm64: dts: qcom: sm8250: provide additional MSI interrupts .../devicetree/bindings/pci/qcom,pcie.yaml | 53 +++- arch/arm64/boot/dts/qcom/sm8250.dtsi | 12 +- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pci-exynos.c | 2 +- .../pci/controller/dwc/pcie-designware-host.c | 243 +++++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 2 +- drivers/pci/controller/dwc/pcie-keembay.c | 2 +- drivers/pci/controller/dwc/pcie-qcom.c | 1 - drivers/pci/controller/dwc/pcie-spear13xx.c | 2 +- drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 10 files changed, 246 insertions(+), 75 deletions(-)