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[v3,0/7] PCI: microchip: Fixes and clean-ups

Message ID 20230728131401.1615724-1-daire.mcnamara@microchip.com (mailing list archive)
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Series PCI: microchip: Fixes and clean-ups | expand

Message

Daire McNamara July 28, 2023, 1:13 p.m. UTC
From: Daire McNamara <daire.mcnamara@microchip.com>

This patch series contains fixes and clean-ups for the Microchip PolarFire SoC PCIe driver

These patches are extracted from the link below to separate them from the outbound and inbound
range handling which is taking considerable time.
Link: https://lore.kernel.org/linux-riscv/20230111125323.1911373-1-daire.mcnamara@microchip.com/

Resending with correct e-mail address list

These patches are regenerated on v6.5-rc3.

Main changes from v2:
- Reworked "Gather MSI information..." as suggested by Bjorn
- merged 'Gather MSI Information..." and "Rename and refactor" as suggested by Bjorn
- Re-generated on v6.5-rc3

Main Changes from v1:
- Dropped "Remove cast warning for devm_add_action_or_reset()". This
  has been overtaken by a patch series from Krzysztof Wilczynski.
- Improved the comment for "Enable building driver as a module" to
  clarify what enables building the driver as a module.
- Split "Gather MSI information from hardware config registers",
  for clarity, into:
   - "Gather MSI information from hardware config registers" purely
      changing the of source of MSI-related information (Num MSIs and
      MSI address) from #defines (which can be incorrect) to FPGA
      configuration registers (which is the ultimate source of truth),
      and a
   - "Rename and refactor ..." patch as a function's code is now clearly
      unrelated to its current name.

cc: Conor Dooley <conor.dooley@microchip.com>
cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
cc: "Krzysztof WilczyƄski" <kw@linux.com>
cc: Rob Herring <robh@kernel.org>
cc: Bjorn Helgaas <bhelgaas@google.com>
cc: linux-riscv@lists.infradead.org
cc: linux-pci@vger.kernel.org

Daire McNamara (8):
  PCI: microchip: Correct the DED and SEC interrupt bit offsets
  PCI: microchip: Enable building driver as a module
  PCI: microchip: Align register, offset, and mask names with hw docs
  PCI: microchip: Enable event handlers to access bridge and ctrl ptrs
  PCI: microchip: Clean up initialisation of interrupts
  PCI: microchip: Gather MSI information from hardware config registers
  PCI: microchip: Re-partition code between probe() and init()

 drivers/pci/controller/Kconfig               |   2 +-
 drivers/pci/controller/pcie-microchip-host.c | 393 +++++++++++--------
 2 files changed, 233 insertions(+), 162 deletions(-)


base-commit: 6eaae198076080886b9e7d57f4ae06fa782f90ef

Comments

Lorenzo Pieralisi Aug. 8, 2023, 11:02 a.m. UTC | #1
On Fri, 28 Jul 2023 14:13:54 +0100, daire.mcnamara@microchip.com wrote:
> This patch series contains fixes and clean-ups for the Microchip PolarFire SoC PCIe driver
> 
> These patches are extracted from the link below to separate them from the outbound and inbound
> range handling which is taking considerable time.
> Link: https://lore.kernel.org/linux-riscv/20230111125323.1911373-1-daire.mcnamara@microchip.com/
> 
> Resending with correct e-mail address list
> 
> [...]

Applied to controller/microchip, thanks!

[1/7] PCI: microchip: Correct the DED and SEC interrupt bit offsets
      https://git.kernel.org/pci/pci/c/6d473a5a2613
[2/7] PCI: microchip: Enable building driver as a module
      https://git.kernel.org/pci/pci/c/2e245bc8a2ab
[3/7] PCI: microchip: Align register, offset, and mask names with hw docs
      https://git.kernel.org/pci/pci/c/4d6bf4c49578
[4/7] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs
      https://git.kernel.org/pci/pci/c/d1d6a0c9e79c
[5/7] PCI: microchip: Clean up initialisation of interrupts
      https://git.kernel.org/pci/pci/c/4f0b91247f78
[6/7] PCI: microchip: Gather MSI information from hardware config registers
      https://git.kernel.org/pci/pci/c/1abb722888fd
[7/7] PCI: microchip: Re-partition code between probe() and init()
      https://git.kernel.org/pci/pci/c/bac406c34fbc

Thanks,
Lorenzo