| Message ID | 20231227094504.32257-1-n.proshkin@yadro.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | pciutils: Add utility for Lane Margining | expand |
On Wed, 27 Dec 2023 14:44:49 +0500 Nikita Proshkin <n.proshkin@yadro.com> wrote: > PCIe Base Spec Rev 4.0 introduced new extended capability mandatory for all > ports - Lane Margining at the Receiver. This new feature allows to get an > approximation of the Link eye margin diagram by four points. This > information shows how resistant the Link is to external influences and can > be useful for link debugging and presets tuning. > Previously, this information was only available using a hardware debugger. > > Patch series consists of two parts: > > * Patch for lspci to add Margining registers reading. There is not much > information available without issuing any margining commands, but this > info is useful anyway; > * New pcilmr utility. > > Patch series is also posted as PR on pciutils github: > https://github.com/pciutils/pciutils/pull/162 > > Changelog: > > v2: > - Replace packed structures with bitfields for margining registers parsing > with BIT() and MASK() macros; > - Hardware quirks are now based on ports PCI ID instead of /proc/cpuinfo; > - Refer to the PCIe Spec properly; > - Clean up the formatting; > - Move the entire internal interface of the utility into one common header; > - Use pcilib u8/16/... types instead of types from stdint.h; > - Use common.c functions such as die() and xmalloc() as Martin suggested; > - Change utility building to the variant with linking object files > separately instead of building lmr as a library. > > v1: > https://lore.kernel.org/linux-pci/20231208091734.12225-1-n.proshkin@yadro.com/ Gently pinging Martin. Review v2 patches, please. I would like to hear any requests/suggestions on them. Thanks. Nikita Proshkin
Hi! Thanks, merged. Martin
PCIe Base Spec Rev 4.0 introduced new extended capability mandatory for all ports - Lane Margining at the Receiver. This new feature allows to get an approximation of the Link eye margin diagram by four points. This information shows how resistant the Link is to external influences and can be useful for link debugging and presets tuning. Previously, this information was only available using a hardware debugger. Patch series consists of two parts: * Patch for lspci to add Margining registers reading. There is not much information available without issuing any margining commands, but this info is useful anyway; * New pcilmr utility. Margining capability assumes the exchange of commands with the device, so its support was implemented as a separate utility pcilmr. The pcilmr allows you to test Links and supports all the features provided by the Margining capability. The utility is written using a pcilib, it is divided into a library part and a main function with arguments parsing in the pciutils root dir. Man page is provided as well. Utility compilation and man page preparation are integrated into the pciutils Makefile, so run make is enough to start testing the utility (16/32 GT/s Link is required though). Utility was written with Linux in mind and was tested only on this OS. Example utility results on different systems you can see in gist: https://gist.github.com/bombanya/f2b15263712757ffba1a11eea011c419 Patch series is also posted as PR on pciutils github: https://github.com/pciutils/pciutils/pull/162 Changelog: v2: - Replace packed structures with bitfields for margining registers parsing with BIT() and MASK() macros; - Hardware quirks are now based on ports PCI ID instead of /proc/cpuinfo; - Refer to the PCIe Spec properly; - Clean up the formatting; - Move the entire internal interface of the utility into one common header; - Use pcilib u8/16/... types instead of types from stdint.h; - Use common.c functions such as die() and xmalloc() as Martin suggested; - Change utility building to the variant with linking object files separately instead of building lmr as a library. v1: https://lore.kernel.org/linux-pci/20231208091734.12225-1-n.proshkin@yadro.com/ Nikita Proshkin (15): pciutils-lspci: Fix unsynchronized caches in lspci struct device and pci struct pci_dev pciutils: Add constants for Lane Margining at the Receiver Extended Capability pciutils-lspci: Add Lane Margining support to the lspci pciutils-pcilib: Add separate file for bit manipulation functions pciutils-pcilmr: Add functions for device checking and preparations before main margining processes pciutils-pcilmr: Add margining process functions pciutils-pcilmr: Add logging functions for margining pciutils-pcilmr: Add function for default margining results log pciutils-pcilmr: Add utility main function pciutils-pcilmr: Add support for unique hardware quirks pciutils-pcilmr: Add the ability to pass multiple links to the utility pciutils-pcilmr: Add --scan mode to search for all LMR-capable Links pciutils-pcilmr: Add option to save margining results in csv form pciutils-pcilmr: Add handling of situations when device reports its MaxOffset values equal to 0 pciutils-pcilmr: Add pcilmr man page Makefile | 16 +- lib/bitops.h | 39 +++ lib/header.h | 7 + lib/pci.h | 1 + lmr/lmr.h | 228 +++++++++++++++++ lmr/margin.c | 573 +++++++++++++++++++++++++++++++++++++++++++ lmr/margin_hw.c | 160 ++++++++++++ lmr/margin_log.c | 158 ++++++++++++ lmr/margin_results.c | 283 +++++++++++++++++++++ ls-ecaps.c | 22 +- lspci.c | 1 + lspci.h | 6 - pcilmr.c | 483 ++++++++++++++++++++++++++++++++++++ pcilmr.man | 182 ++++++++++++++ 14 files changed, 2149 insertions(+), 10 deletions(-) create mode 100644 lib/bitops.h create mode 100644 lmr/lmr.h create mode 100644 lmr/margin.c create mode 100644 lmr/margin_hw.c create mode 100644 lmr/margin_log.c create mode 100644 lmr/margin_results.c create mode 100644 pcilmr.c create mode 100644 pcilmr.man -- 2.34.1