| Message ID | 20240510073710.98953-1-kobayashi.da-06@fujitsu.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | cxl: Export cxl1.1 device link status to sysfs | expand |
Kobayashi Daisuke wrote: > > Export cxl1.1 device link status register value to pci device sysfs. > > CXL devices are extensions of PCIe. Therefore, from CXL2.0 onwards, > the link status can be output in the same way as traditional PCIe. > However, unlike devices from CXL2.0 onwards, CXL1.1 requires a > different method to obtain the link status from traditional PCIe. > This is because the link status of the CXL1.1 device is not mapped > in the configuration space (as per cxl3.0 specification 8.1). > Instead, the configuration space containing the link status is mapped > to the memory mapped register region (as per cxl3.0 specification 8.2, > Table 8-18). Therefore, the current lspci has a problem where it does > not display the link status of the CXL1.1 device. > Solve these issues with sysfs attributes to export the status > registers hidden in the RCRB. > > The procedure is as follows: > First, obtain the RCRB address within the cxl driver, then access > the configuration space. Next, output the link status information from > the configuration space to sysfs. Ultimately, the expectation is that > this sysfs file will be consumed by PCI user tools to utilize link status > information. > > > Changes > v1[1] -> v2: > - Modified to perform rcrb access within the CXL driver. > - Added new attributes to the sysfs of the PCI device. > - Output the link status information to the sysfs of the PCI device. > - Retrieve information from sysfs as the source when displaying information in > lspci. > > v2[2] -> v3: > - Fix unnecessary initialization and wrong types (Bjohn). > - Create a helper function for getting a PCIe capability offset (Bjohn). > - Move platform-specific implementation to the lib directory in pciutils > (Martin). > > v3[3] -> v4: > - RCRB register values are read once and cached. > - Added a new attribute to the sysfs of the PCI device. > - Separate lspci implementation from this patch. > > v4[4] -> v5: > - Use macros for bitwise operations > - Fix RCRB access to use cxl_memdev > > v5[5] -> v6: > - Add and use masks for RCRB register values > > v6[6] -> v7: > - Fix comments on white space inline > > [1] > https://lore.kernel.org/linux-cxl/20231220050738.178481-1-kobayashi.da-06 > @fujitsu.com/ > [2] > https://lore.kernel.org/linux-cxl/20240227083313.87699-1-kobayashi.da-06@ > fujitsu.com/ > [3] > https://lore.kernel.org/linux-cxl/20240312080559.14904-1-kobayashi.da-06@ > fujitsu.com/ > [4] > https://lore.kernel.org/linux-cxl/20240409073528.13214-1-kobayashi.da-06@ > fujitsu.com/ > [5] > https://lore.kernel.org/linux-cxl/20240412070715.16160-1-kobayashi.da-06@ > fujitsu.com/ > [6] > https://lore.kernel.org/linux-cxl/20240424050102.26788-1-kobayashi.da-06@ > fujitsu.com/ > > Kobayashi,Daisuke (2): > cxl: Add rcd_regs to cxl_rcrb_info > cxl/pci: Add sysfs attribute for CXL 1.1 device link statu > > drivers/cxl/core/core.h | 4 ++ > drivers/cxl/core/regs.c | 16 +++++++ > drivers/cxl/cxl.h | 3 ++ > drivers/cxl/pci.c | 101 > ++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 124 insertions(+) > > -- > 2.44.0 Hi all. Gentle ping. Is there anything I can do to help with merging the patch? I believe I have addressed all of the points raised in the review.