| Message ID | 20240701215020.3813275-1-dave.jiang@intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | cxl: Region bandwidth calculation for targets with shared upstream link | expand |
On Mon, Jul 01, 2024 at 02:49:13PM -0700, Dave Jiang wrote: > v6: > - Update kdoc in comments. (Ira) > - Various rearranging and cleanup of variable declarations. (Jonathan) Housekeeping nit: it's helpful to include the diffstat in the cover letter so I can tell whether I need to look at this, e.g., does it affect the subsystem I worry about? Also nice to have URLs and the brief changelog for previous versions.
On 7/2/24 9:47 AM, Bjorn Helgaas wrote: > On Mon, Jul 01, 2024 at 02:49:13PM -0700, Dave Jiang wrote: >> v6: >> - Update kdoc in comments. (Ira) >> - Various rearranging and cleanup of variable declarations. (Jonathan) > > Housekeeping nit: it's helpful to include the diffstat in the cover > letter so I can tell whether I need to look at this, e.g., does it > affect the subsystem I worry about? Also nice to have URLs and the > brief changelog for previous versions. > Thanks Bjorn. Will do. stgit email used to include the diff stat. Not sure why they dropped the diff stats addition when they went to rust from python.
v6: - Update kdoc in comments. (Ira) - Various rearranging and cleanup of variable declarations. (Jonathan) This series provides recalculation of the CXL region bandwidth when the targets have shared upstream link by walking the toplogy from bottom up and clamp the bandwdith as the code traverses up the tree. An example topology: An example topology from Jonathan: CFMWS 0 | _________|_________ | | ACPI0017-0 ACPI0017-1 GP0/HB0/ACPI0016-0 GP1/HB1/ACPI0016-1 | | | | RP0 RP1 RP2 RP3 | | | | SW 0 SW 1 SW 2 SW 3 | | | | | | | | EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7 Computation for the example topology: Min (GP0 to CPU BW, Min(SW 0 Upstream Link to RP0 BW, Min(SW0SSLBIS for SW0DSP0 (EP0), EP0 DSLBIS, EP0 Upstream Link) + Min(SW0SSLBIS for SW0DSP1 (EP1), EP1 DSLBIS, EP1 Upstream link)) + Min(SW 1 Upstream Link to RP1 BW, Min(SW1SSLBIS for SW1DSP0 (EP2), EP2 DSLBIS, EP2 Upstream Link) + Min(SW1SSLBIS for SW1DSP1 (EP3), EP3 DSLBIS, EP3 Upstream link))) + Min (GP1 to CPU BW, Min(SW 2 Upstream Link to RP2 BW, Min(SW2SSLBIS for SW2DSP0 (EP4), EP4 DSLBIS, EP4 Upstream Link) + Min(SW2SSLBIS for SW2DSP1 (EP5), EP5 DSLBIS, EP5 Upstream link)) + Min(SW 3 Upstream Link to RP3 BW, Min(SW3SSLBIS for SW3DSP0 (EP6), EP6 DSLBIS, EP6 Upstream Link) + Min(SW3SSLBIS for SW3DSP1 (EP7), EP7 DSLBIS, EP7 Upstream link))))