| Message ID | 20240827063631.3932971-1-quic_qianyu@quicinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for PCIe3 on x1e80100 | expand |
On Mon, 26 Aug 2024 23:36:23 -0700, Qiang Yu wrote: > This series add support for PCIe3 on x1e80100. > > PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP > PHY configuration compare other PCIe instances on x1e80100. Hence add > required resource configuration and usage for PCIe3. > > Qiang Yu (8): > phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets > phy: qcom-qmp: pcs: Add v6.30 register offsets > phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 > arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 > dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 > QMP PCIe PHY Gen4 x8 > clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks > arm64: dts: qcom: x1e80100-qcp: Add power supply and sideband signal > for pcie3 > PCI: qcom: Add support to PCIe slot power supplies > > .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 18 +- > arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 116 +++++++++ > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 +++++++++++++++- > drivers/clk/qcom/gcc-x1e80100.c | 10 +- > drivers/pci/controller/dwc/pcie-qcom.c | 52 +++- > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 222 +++++++++++++++++- > .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 ++ > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ > 8 files changed, 657 insertions(+), 10 deletions(-) > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h > create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h > > -- > 2.34.1 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y qcom/x1e80100-qcp.dtb' for 20240827063631.3932971-1-quic_qianyu@quicinc.com: arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: reg: [[0, 29163520, 0, 12288], [0, 2013265920, 0, 3869], [0, 2013269824, 0, 168], [0, 2013270016, 0, 4096], [0, 2014314496, 0, 1048576]] is too short from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: reg-names: ['parf', 'dbi', 'elbi', 'atu', 'config'] is too short from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clocks: [[53, 348], [53, 84], [53, 86], [53, 87], [53, 94], [53, 95], [53, 22], [53, 33]] is too long from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:0: 'aux' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:1: 'cfg' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:2: 'bus_master' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:3: 'bus_slave' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:4: 'slave_q2a' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:5: 'noc_aggr' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names:6: 'cnoc_sf_axi' was expected from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: clock-names: ['pipe_clk_src', 'aux', 'cfg', 'bus_master', 'bus_slave', 'slave_q2a', 'noc_aggr', 'cnoc_sf_axi'] is too long from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pci@1bd0000: Unevaluated properties are not allowed ('operating-points-v2', 'opp-table' were unexpected) from schema $id: http://devicetree.org/schemas/pci/qcom,pcie-x1e80100.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@1be0000: clock-names:4: 'pipe' was expected from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@1be0000: clock-names:5: 'pipediv2' was expected from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: phy@1be0000: clock-names:6: 'phy_aux' was expected from schema $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@3: gpio@8800: 'pm_sde7_aux_3p3', 'pm_sde7_main_3p3' do not match any of the regexes: '-hog(-[0-9]+)?$', '-state$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: gpio@8800: 'pm_sde7_aux_3p3', 'pm_sde7_main_3p3' do not match any of the regexes: '-hog(-[0-9]+)?$', '-state$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: pmic@8: gpio@8800: 'pcie_x8_12v_on' does not match any of the regexes: '-hog(-[0-9]+)?$', '-state$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/qcom,spmi-pmic.yaml# arch/arm64/boot/dts/qcom/x1e80100-qcp.dtb: gpio@8800: 'pcie_x8_12v_on' does not match any of the regexes: '-hog(-[0-9]+)?$', '-state$', 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/pinctrl/qcom,pmic-gpio.yaml#
This series add support for PCIe3 on x1e80100. PCIe3 needs additional set of clocks, regulators and new set of PCIe QMP PHY configuration compare other PCIe instances on x1e80100. Hence add required resource configuration and usage for PCIe3. Qiang Yu (8): phy: qcom-qmp: pcs-pcie: Add v6.30 register offsets phy: qcom-qmp: pcs: Add v6.30 register offsets phy: qcom: qmp: Add phy register and clk setting for x1e80100 PCIe3 arm64: dts: qcom: x1e80100: Add support for PCIe3 on x1e80100 dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the X1E80100 QMP PCIe PHY Gen4 x8 clk: qcom: gcc-x1e80100: Fix halt_check for pipediv2 clocks arm64: dts: qcom: x1e80100-qcp: Add power supply and sideband signal for pcie3 PCI: qcom: Add support to PCIe slot power supplies .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 18 +- arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 116 +++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 205 +++++++++++++++- drivers/clk/qcom/gcc-x1e80100.c | 10 +- drivers/pci/controller/dwc/pcie-qcom.c | 52 +++- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 222 +++++++++++++++++- .../qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h | 25 ++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h | 19 ++ 8 files changed, 657 insertions(+), 10 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_30.h create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_30.h